Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 132 of 198
Min_and_max_level (port-1)*0x100+ts*8+4
Bits Data Element Name R/W
Reset
Value
Description
[15:10]
Reserved
RO
0x00
These bits are always zero
[9:0]
Maximal_level
RO
None
The maximal level that the jitter buffer has reached since
the last time this register was read. After this register is
read the TDMoP block resets this field to zero. When
overrun is reached, the value remains equal to
Rx_max_buff_size until it is read by the CPU. The
resolution is 0.5 ms.
11.4.8.2.2 Unstructured AAL1/SAToP
Min_and_max_level (port-1)*0x100+4
Bits Data Element Name R/W
Reset
Value
Description
[31]
Reserved
RO
0x0
This bit is always zero
[30:16]
Minimal_level
RO
None
The minimal level that the jitter buffer has reached since
the last time this register was read. After this register is
read the TDMoP block resets this field to all ones. When
underrun is reached, the value of this field remains zero
until it is read by the CPU. The resolution is 32 interface
bit periods.
[15]
Reserved
RO
0x0
This bit is always zero
[14:0]
Maximal_level
RO
None
The maximal level that the jitter buffer has reached since
the last time this register was read. After this register is
read the TDMoP block resets this field to zero. When
overrun is reached, the value remains equal to
Rx_max_buff_size until it is read by the CPU. The
resolution is 32 interface bit periods.
11.4.8.2.3 High Speed AAL1/SAToP
Min_and_max_level 0x004
Bits Data Element Name R/W
Reset
Value
Description
[31:16]
Minimal_level
RO
0xFFFF
The 16 MSbs of the minimal level that the jitter buffer has
reached since the last time this register was read. After
this register is read the TDMoP block resets this field to all
ones. When underrun is reached, the value of this field
remains zero until it is read by the CPU. The level is 17
bits wide. The resolution is 64 interface bit periods.
[15:0]
Maximal_level
RO
0x0000
The 16 MSbs of the maximal level that the jitter buffer has
reached since the last time this register was read. After
this register is read the TDMoP block resets this field to
zero. When overrun is reached, the value remains equal
to
Rx_max_buff_size until it is read by the CPU. The level
is 17 bits wide. The resolution is 64 interface bit periods.
11.4.8.3 Bundle Timeslot Registers
In this section, the index n indicates the bundle number: 0 to 63.
Bundle_ts[n] 0xF00+n*4
Bits Data Element Name R/W
Reset
Value
Description
[31:0]
Ts_assigned
R/W
None
Assigned timeslots of the bundle. See section 10.6.10.
1 = Timeslot is assigned to the bundle
0 = Timeslot is not assigned to the bundle