Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 127 of 198
11.4.6.5 ETH- to-CPU Queue
ETH_to_CPU_q_read 0x30 (0x32)
Bits Data Element Name R/W
Reset
Value
Description
[31:13]
Reserved
-
0x0
Must be set to zero
[12:0]
Buffer ID
RO
None
Reading from this address extracts the first buffer ID from
the ETH-to-CPU queue (bits [12:0]). The buffer ID serves
as the 13 MSbs of the buffer address in the SDRAM (i.e.
corresponds to
H_AD[23:11] out of 24 SDRAM address
bits).
ETH_to_CPU_q_level 0x34 (0x36)
Bits Data Element Name R/W
Reset
Value
Description
[31:8]
Reserved
-
0x0
Must be set to zero
[7:0]
Level
RO
0x0
Number of buffers currently stored in the queue. These
are the buffers still waiting to be handled by the CPU.
Range: 0 to 128.
ETH_to_CPU_q_thresh 0x38 (0x3A)
Bits Data Element Name R/W
Reset
Value
Description
[31:8]
Reserved
-
0x0
Must be set to zero
[7:0]
Threshold
RO
0x0
If the number of buffers in the queue is ≥ this threshold,
an interrupt is generated. Range: 0 to 128.
11.4.6.6 CPU-to-TDM Queue
CPU_to_TDM_q_insert 0x54 (0x56)
Bits Data Element Name R/W
Reset
Value
Description
[31:13]
Reserved
-
0x0
Must be set to zero
[12:0]
Buffer ID
WO
None
Writing to this address causes a single 13-bit buffer ID to
be inserted to the CPU-to-TDM queue. Only bits [12:0] are
written. The buffer ID serves as the 13 MSbs of the buffer
address in the SDRAM (i.e. corresponds to
H_AD[23:11]
out of the 24 SDRAM address bits).
CPU_to_TDM_q_level 0x58 (0x5A)
Bits Data Element Name R/W
Reset
Value
Description
[31:6]
Reserved
-
0x0
Must be set to zero
[5:0]
Level
RO
0x0
Number of buffers currently stored in the queue. Range: 0
to 32.
CPU_to_TDM_q_thresh 0x5C (0x5E)
Bits Data Element Name R/W
Reset
Value
Description
[31:6]
Reserved
-
0x0
Must be set to zero
[5:0]
Threshold
RO
0x0
If the number of buffers in the queue is ≥ this threshold,