Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 124 of 198
11.4.6 CPU Queues
The pools and queue referred to in this section are shown in the block diagram in Figure 10-49. Whenever a queue
or pool level exceeds the associated threshold register, a latched status bit is set in the CPU_Queues_change
register which generates an interrupt unless masked by the associated mask bit in the CPU_Queues_mask
register.
In this section the address offsets in parentheses apply when the CPU data bus is 16 bits wide (pin
DAT_32_16_N=0). The base address for the TDMoP CPU queues is 0x20,000.
Table 11-7. CPU Queues
Addr
Offset
Register Name Description Page
0x00 (0x02)
TDM_to_CPU_pool_insert
Write to insert a buffer ID into the TDM-to-CPU Pool
124
0x04 (0x06)
TDM_to_CPU_pool_level
Number of buffers stored in the TDM-to-CPU Pool
125
0x08 (0x0A)
TDM_to_CPU_pool_thresh
TDM-to-CPU Pool interrupt threshold
125
0x0C (0x0E)
TDM_to_CPU_q_read
Read to get a buffer ID from the TDM-to-CPU Queue
125
0x10 (0x12)
TDM_to_CPU_q_level
Number of buffers in the TDM-to-CPU Queue
125
0x14 (0x16)
TDM_to_CPU_q_thresh
TDM-to-CPU Queue interrupt threshold
125
0x18 (0x1A)
CPU_to_ETH_q_insert
Write to insert a buffer ID into the CPU-to-ETH Queue
125
0x1C (0x1E)
CPU_to_ETH_q_level
Number of buffers in the CPU-to-ETH Queue
126
0x20 (0x22)
CPU_to_ETH_q_thresh
CPU-to-ETH Queue interrupt threshold
126
0x24 (0x26)
ETH_to_CPU_pool_insert
Write to insert a buffer ID into the ETH-to-CPU Pool
126
0x28 (0x2A)
ETH_to_CPU_pool_level
Number of buffers stored in the ETH-to-CPU Pool
126
0x2C (0x2E)
ETH_to_CPU_pool_thresh
ETH-to-CPU Queue interrupt threshold.
126
0x30 (0x32)
ETH_to_CPU_q_read
Read to get a buffer ID from the ETH-to-CPU Queue
127
0x34 (0x36)
ETH_to_CPU_q_level
Number of buffers in the ETH-to-CPU Queue.
127
0x38 (0x3A)
ETH_to_CPU_q_thresh
ETH-to-CPU Queue interrupt threshold
127
0x54 (0x56)
CPU_to_TDM_q_insert
Write to insert a buffer ID into the CPU-to-TDM Queue
127
0x58 (0x5A)
CPU_to_TDM_q_level
Number of buffers stored in the CPU-to-TDM Queue
127
0x5C (0x5E)
CPU_to_TDM_q_thresh
CPU-to-TDM Queue interrupt threshold
127
0x60 (0x62)
Tx_return_q_read
Read to get a buffer ID from the CPU-tx-return Queue
128
0x64 (0x66)
Tx_return_q_level
Number of buffers stored in the CPU-tx-return Queue
128
0x68 (0x6A)
Tx_return_q_thresh
CPU-tx-return Queue interrupt threshold
128
0x6C (0x6E)
Rx_return_q_read
Read to get a buffer ID from the CPU-rx-return Queue
128
0x70 (0x72)
Rx_return_q_level
Number of buffers stored in the CPU-rx-return Queue
129
0x74 (0x76)
Rx_return_q_thresh
CPU-rx-return Queue interrupt threshold
129
11.4.6.1 TDM-to-CPU Pool
TDM_to_CPU_pool_insert 0x00 (0x02)
Bits Data Element Name R/W
Reset
Value
Description
[31:13]
Reserved
-
0x0
Must be set to zero
[12:0]
Buffer ID
WO
None
Writing to this address causes a single 13-bit buffer ID to
be inserted to the TDM-to-CPU pool. Only bits [12:0] are
written. The buffer ID serves as the 13 MSbs of the buffer
address in the SDRAM (i.e. corresponds to
H_AD[23:11]
out of the 24 SDRAM address bits).