Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 119 of 198
11.4.3.2 Per Jitter Buffer Index Counters
In the register description in this section, the index n indicates the jitter buffer number: 0 to 255.
Jitter Buffer Underrun/Overrun Events Counter 0x800+n*4
Bits Data Element Name R/W
Reset
Value
Description
[31:8]
Reserved
-
None
Must be set to zero
[7:0]
JBC_events
R
None
Number of jitter buffer underrun/overrun events.
AAL1/SAToP/CESoPSN bundles – count of underrun
events. AAL1 counter does not include underruns caused
by pointer mismatches.
HDLC bundles – count of overrun events.
Counter sticks at its maximum value and does not roll
over to 0.
11.4.3.3 General Counters
Received Ethernet Bytes Counter 0xE00
Bits Data Element Name R/W
Reset
Value
Description
[31:0]
ETH_bytes_received
R
0x0000
0000
Total bytes received from Ethernet (good packets which
passed CRC check only). CRC bytes are not counted.
Counter wraps around to 0 from its maximum value.
Transmitted Ethernet Bytes Counter 0xE04
Bits Data Element Name R/W
Reset
Value
Description
[31:0]
ETH_bytes_transmitted
R
0x0000
0000
Total bytes transmitted to Ethernet (good packets which
passed CRC check only). CRC bytes are not counted.
Counter wraps around to 0 from its maximum value.
Classified Packets Counter 0xE08
Bits Data Element Name R/W
Reset
Value
Description
[31:0]
Classified_packets
R
0x0000
0000
Counts all packets that pass the packet classifier towards
TDM or CPU and are not discarded.
Counter wraps around to 0 from its maximum value.
Received IP Checksum Errors Counter 0xE0C
Bits Data Element Name R/W
Reset
Value
Description
[31:16]
Reserved
-
0x0000
Must be set to zero
[15:0]
IP_checksum_err_packets
R
0x0000
Counts packets, detected by the packet classifier, as
packets with IP checksum errors.
Counter sticks at its maximum value and does not roll
over to 0.