Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 113 of 198
HDLC_Bundle[n]_cfg[127:96] 0x300+n*4
Bits Data Element Name R/W
Reset
Value
Description
00 = No cookies in the TX L2TPv3 header
01 = One cookie in the TX L2TPv3 header
10 = Two cookies in the TX L2TPv3 header
11 = Reserved
[7:4] Port_num R/W
None
The port number which the bundle is assigned to:
0000 = Port 1, 0111=Port 8
[3:2] Tx_VLAN_stack R/W
None
00 = No VLAN tag in header
01 = One VLAN tag exists in header
10 = Two VLAN tags exist in header
11 = Reserved
Not valid for Rx. Not used by Tx AAL1 but by Ethernet
MAC transmit block
[1] Rx_Bundle_Identifier_valid R/W
None
0 = Rx_bundle_identifier entry isn't valid: If the incoming
frame bundle identifier isn't found in the whole packet
classifier table, the incoming frame is handled
according to discard switches in
(
Packet_classifier_cfg_reg3)
1 = Rx_Bundle_Identifier entry is valid
[0]
Reserved
R/W
None
Must be set to zero
HDLC_Bundle[n]_cfg[159:128] 0x400+n*4
Bits Data Element Name R/W
Reset
Value
Description
[31:22]
Reserved
0x000
Must be set to zero
[21:20] Rx_L2TPV3_cookies R/W
None
For MPLS:
00 = Reserved
01 = One label in the received MPLS stack
10 = Two label in the received MPLS stack
11 = Three label in the received MPLS stack
For L2TPv3:
00 = No cookies in the received L2TPv3 header
01 = One cookie in the received L2TPv3 header
10 = Two cookies in the received L2TPv3 header
11 = Reserved
[19:16]
Reserved
R/W
None
[15:0] Tx_IP_checksum R/W
None
IP header checksum for IP total length equal to zero
Explain more. Also, why isn’t this in AAL1?
11.4.2.3 SAToP/CESoPSN Bundle Configuration
In the register descriptions below, the index n indicates bundle number: 0 to 63.
SAToP/CESoPSN_Bundle[n]_cfg[31:0] 0x000+n*4
Bits Data Element Name R/W
Reset
Value
Description
[31:0]
Rx_bundle_identifier
R/W
None
Holds the Rx bundle number
SAToP/CESoPSN_Bundle[n]_cfg[63:32] 0x100+n*4
Bits Data Element Name R/W
Reset
Value
Description
[31:22] Rx_max_buff_size R/W None
The size of the jitter buffer. See section 10.6.10. Also the
maximum time interval for which data is stored. The
resolution is determined by the interface type as follows:
For framed E1/T1: 0.5 ms.