Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 111 of 198
AAL1_Bundle[n]_cfg[127:96] 0x300+n*4
Bits Data Element Name R/W
Reset
Value
Description
00 = No cookies in the TX L2TPv3 header
01 = One cookie in the TX L2TPv3 header
10 = Two cookies in the TX L2TPv3 header
11 = Reserved
[7:4] Port_num R/W None
The port number which the bundle is assigned to:
0000 = Port 1, 0111=Port 8
[3:2] Tx_VLAN_stack R/W None
00 = No VLAN tag in header
01 = One VLAN tag exists in header
10 = Two VLAN tags exist in header
11 = Reserved
Not valid for Rx. Not used by Tx AAL1 but by Ethernet
transmitter block
[1] Rx_bundle_identifier_valid R/W None
0 = Rx_bundle_identifier entry isn't valid: If the incoming
frame bundle identifier isn't found in the whole packet
classifier table, the incoming frame is handled
according to packet classifier discard switches in
Packet_classifier_cfg_reg3.
1 = Rx_Bundle_Identifier entry is valid
[0]
Reserved
R/W
None
Must be set to zero
AAL1_Bundle[n]_cfg[159:128] 0x400+n*4
Bits Data Element Name R/W
Reset
Value
Description
[31:23]
Reserved
R/W
None
Must be set to zero
[22] Rx_RTP R/W None
0 = RTP header does not exist in received packets
1 = RTP header exists in received packets
[21:20] Rx_L2TPV3_cookies R/W None
For MPLS:
00 = Reserved
01 = One label in the received MPLS stack
10 = Two label in the received MPLS stack
11 = Three label in the received MPLS stack
For L2TPv3:
00 = No cookies in the received L2TPv3 header
01 = One cookie in the received L2TPv3 header
10 = Two cookies in the received L2TPv3 header
11 = Reserved
[19:15]
Reserved
R/W
None
Must be set to zero.
[14:10]
Packet_size_in_cells
R/W
None
AAL1 SAR PDUs per frame: 1 - 30
[9:5] Tx_bundle_identifier R/W None
Tx bundle Identifier upper bits
Used only for TX_AAL1 old format
[4:0]
Reserved
R/W
None
Must be set to zero
11.4.2.2 HDLC Bundle Configuration
In the register descriptions below, the index n indicates the bundle number: 0 to 63.
HDLC_Bundle[n]_cfg[31:0] 0x000+n*4
Bits Data Element Name R/W
Reset
Value
Description
[31:0]
Rx_bundle_identifier
R/W
None
Holds the Rx bundle number
HDLC_Bundle[n]_cfg[63:32] 0x100+n*4
Bits Data Element Name R/W
Reset
Value
Description
[31:22]
Reserved
R/W
None
Must be set to zero