Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 107 of 198
11.4.1.2 TDMoP Status Registers
The General_stat_reg register has latched status registers that indicate hardware events. For each bit, the value 1
indicates that the event occurred. Writing 1 to a bit clears it to 0. Writing 0 to a bit does not change its value.
General_stat_reg 0xE0
Bits Data Element Name R/W
Reset
Value
Description
[31:10]
Reserved
-
0x0
Must be set to zero
[9]
MAC_Rx_fifo_overrun
R/W
0x0
MAC Rx FIFO overflowed
[8] Ipver_err_status
R/W
0x0
Indicates that a packet was discarded due to IP version
error
[7]
Rx_fifo_sof_err
R/W
0x0
Rx FIFO was flushed due to bundle configuration error
[6] TDM_CPU_buff_err
R/W
0x0
Frames received from TDM discarded due to lack of
buffers at TDM TO CPU pool
[5] Rx_fifo_full
R/W
0x0
Packet received from Ethernet discarded because Rx
FIFO is full
[4]
MPLS_err
R/W
0x0
Received MPLS packet with more than three labels
[3] OAM_ETH_to_CPU_q_full
R/W
0x0
OAM packet received from Ethernet and destined to CPU
discarded because ETH TO CPU queue is full.
[2] OAM_SW_buff_err
R/W
0x0
OAM packet received from Ethernet and destined to CPU
discarded due to lack of SW buffers
[1] Non_OAM_ETH_to_CPU_q_full
R/W
0x0
Non-OAM packet received from Ethernet and destined to
CPU discarded because ETH TO CPU queue is full.
[0] Non_OAM_SW_buff_err
R/W
0x0
Non-OAM packet received from Ethernet and destined to
CPU discarded due to lack of SW buffers.
Version_reg 0xE4
Bits Data Element Name R/W
Reset
Value
Description
[31:0] Chip_version_reg R/O
0xABCD
EF01
Contains the chip version for the TDMoP block
The Port[n]_sticky_reg1 register has latched status bits that indicate port hardware events. For each bit, the value 1
indicates that the event occurred. Writing 1 to a bit clears it to 0. Writing 0 to a bit does not change its value. The
index n indicates port number: 1-8 for DS34S108, 1-4 for DS34S104, 1-2 for DS34S102, 1 only for DS34S101.
Port[n]_sticky_reg1 0xE4+n*4
Bits Data Element Name R/W
Reset
Value
Description
[31:8]
Reserved
-
0x0
Must be set to zero
[7]
Dpll_ovrflow
R/W
0x0
Port clock recovery DPLL overflowed
[6] Cdc_detected R/W 0x0
Port clock recovery detected constant delay change in the
network
[5]
Smart_self_test_failed
R/W
0x0
Provided for debug purposes
[4]
Smart_timeout_expired
R/W
0x0
Provided for debug purposes
[3]
Sticky_filter_ovrflow
R/W
0x0
Port clock recovery loop filter overflowed
[2] Virtual_jitter_buffer_or_ur R/W 0x0
Port clock recovery virtual jitter buffer reached overrun/
underrun state
[1]
Reacquisition_alarm
R/W
0x0
Provided for debug purposes
[0]
Adapt_freeze_state
R/W
0x0
Port clock recovery mechanism is in freeze state