Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 103 of 198
Packet_classifier_cfg_reg3 0x44
Bits Data Element Name R/W
Reset
Value
Description
[16] Discard_switch_0 R/W 0x0
ARP packets whose IP destination address does not
match chip’s addresses. See section 10.6.13.
0 = Forward to CPU
1 = Discard
[15:0] MAC_add1 R/W 0x0000
This field holds bits 47:32 of the first of two MAC
addresses for the device. The lower bits of this MAC
address are in
Packet_classifier_cfg_reg2. The other
MAC address is in Packet_classifier_cfg_reg5 and
Packet_classifier_cfg_reg6
. Relevant only for packets
received from Ethernet port.
Packet_classifier_cfg_reg4 0x48
Bits Data Element Name R/W
Reset
Value
Description
[31:16] TDMoIP_port_num2 R/W 0x085E
Packets with UDP destination port number equal to this
field are recognized as TDMoIP packets. See section
10.6.13.1.
[15:0] TDMoIP_port_num1 R/W 0x085E
Packets with UDP destination port number equal to this
field are recognized as TDMoIP packets. See section
10.6.13.1.
Packet_classifier_cfg_reg5 0x4C
Bits Data Element Name R/W
Reset
Value
Description
[31:0] MAC_add2 R/W 0x0
This field holds bits 31:0 of the second of two MAC
addresses for the device. The upper bits of this MAC
address are in
Packet_classifier_cfg_reg6. The other
MAC address is in Packet_classifier_cfg_reg2 and
Packet_classifier_cfg_reg3
. Relevant only for packets
received from Ethernet port.
Packet_classifier_cfg_reg6 0x50
Bits Data Element Name R/W
Reset
Value
Description
[31:16] Ip_udp_bn_mask_n R/W 0x0000
This mask Indicates the width of the bundle identifier. For
example, if the desired width is 8 bits, the following should
be written to this field: 0000000011111111b. See section
10.6.13.2.
[15:0] MAC_add2 R/W 0x0000
This field holds bits 47:32 of the second of two MAC
addresses for the device. The lower bits of this MAC
address are in
Packet_classifier_cfg_reg5. The other
MAC address is in Packet_classifier_cfg_reg2 and
Packet_classifier_cfg_reg3
. Relevant only for packets
received from Ethernet port.
Packet_classifier_cfg_reg7 0x54
Bits Data Element Name R/W
Reset
Value
Description
[31:16] CPU_dest_ether_type R/W 0x0800
Ethertype which identifies packets destined for the CPU.
Such packets are sent to CPU or discarded as specified
by
Packet_classifier_cfg_reg3.Discard_switch_[8:0].
This field must be set to a value greater than 0x5DC. See