Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 101 of 198
The TDM_cond_data_reg register below holds four octets to be transmitted as conditioning data in the TDM
direction during jitter buffer underrun. This data applies to all bundle types.
TDM_cond_data_reg 0x30
Bits Data Element Name R/W
Reset
Value
Description
[31:24] TDM_cond_octet_a R/W 0x00
TDM Conditioning Octet A
Must be set to 0x7E for HDLC bundles
Also used in high-speed mode
[23:16] TDM_cond_octet_b R/W 0x00
TDM Conditioning Octet B
Must be set to 0x7E for HDLC bundles
[15:8] TDM_cond_octet_c R/W 0x00
TDM Conditioning Octet C
Must be set to 0x7E for HDLC bundles
[7:0] TDM_cond_octet_d R/W 0x00
TDM Conditioning Octet D
Must be set to 0x7E for HDLC bundles
The ETH_cond_data_reg register below holds four octets to be transmitted as conditioning data towards the packet
network (i.e. toward the Ethernet MAC) when no valid data is available from the TDM port. This applies only to
AAL1 or SAToP/CESoPSN bundles. Tx_cond_octet_type in the Bundle Configuration Tables specifies which of
these octets is used on a per-bundle basis.
ETH_cond_data_reg 0x34
Bits Data Element Name R/W
Reset
Value
Description
[31:24]
ETH_cond_octet_d
R/W
0x00
Ethernet Conditioning octet D
[23:16]
ETH_cond_octet_c
R/W
0x00
Ethernet Conditioning octet C
[15:8]
ETH_cond_octet_b
R/W
0x00
Ethernet Conditioning octet B
[7:0]
ETH_cond_octet_a
R/W
0x00
Ethernet Conditioning octet A
Packet_classifier_cfg_reg0 0x38
Bits Data Element Name R/W
Reset
Value
Description
[31:0] Ipv4_add1 R/W 0x0
This field holds the first of three IPv4 addresses for the
device. The other addresses are held in register
Packet_classifier_cfg_reg1 and
Packet_classifier_cfg_reg8
. Relevant only for packets
received from the Ethernet port.
Packet_classifier_cfg_reg1 0x3C
Bits Data Element Name R/W
Reset
Value
Description
[31:0] Ipv4_add2 R/W 0x0
This field holds the second of three IPv4 addresses for the
device. The other addresses are held in register
Packet_classifier_cfg_reg0 and
Packet_classifier_cfg_reg8
. Relevant only for packets
received from the Ethernet port.
Packet_classifier_cfg_reg2 0x40
Bits Data Element Name R/W
Reset
Value
Description
[31:0] MAC_add1 R/W 0x0
This field holds bits 31:0 of the first of two MAC addresses
for the device. The upper bits of this MAC address are in
Packet_classifier_cfg_reg3. The other MAC address is in
Packet_classifier_cfg_reg5 and