Datasheet

____________________________________________________ DS34S101, DS34S102, DS34S104, DS34S108
Rev: 032609 100 of 198
Rst_reg 0x2C
Bits Data Element Name R/W
Reset
Value
Description
[31:28]
Reserved
-
0x0
Must be set to zero
[27:24] Rst_tx_port_num R/W 0x0
Port number associated with Rst_tx field (below).
0000 = Port 1
0001 = Port 2
0010 = Port 3
0011 = Port 4
0100 = Port 5
0101 = Port 6
0110 = Port 7
0111 = Port 8
[23:18]
Rst_tx_internal_bundle_num
R/W
0x00
Bundle number associated with Rst_tx field (below)
[17] Rst_tx_open/close R/W 0x0
Valid when Rst_tx is set
0 = When Rst_tx is done during bundle close procedure
1 = When Rst_tx is done during bundle open procedure
This bit is also used in high-speed mode.
[16] Rst_tx R/W 0x0
If set, the relevant transmit payload type machine resets
its variables (should be given with bundle number and a
proper value of the RST_tx_open/close bit). The CPU
should poll this bit until it is 0 meaning, “reset
acknowledged”. This bit is also used in high-speed mode.
[15:7]
Reserved
R/W
0x0
Must be set to zero
[6:1]
Rst_rx_internal_bundle_num
R/W
0x00
Bundle number associated with Rst_rx
[0] Rst_rx
R/
set
0x0
1 = Packet classifier generates a reset frame
(Rst_rx_internal_bundle_num is valid). The CPU should
poll this bit until it finds 0; this means “reset
acknowledged”.