Datasheet

DS3232M
±5ppm, I
2
C Real-Time Clock with SRAM
4Maxim Integrated
Note 2: Limits are 100% tested at T
A
= +25°C and T
A
= +85°C. Limits over the operating temperature range and relevant supply
voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 3: Includes the temperature conversion current (averaged).
Note 4: Does not include RST leakage if V
CC
< V
PF
.
Note 5: The parameter t
OSF
is the period of time the oscillator must be stopped for the OSF flag to be set.
Note 6: The state of RST does not affect the I
2
C interface or RTC functions.
Note 7: Interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with standard mode
I
2
C timing.
Note 8: C
B
= total capacitance of one bus line in picofarads.
Note 9: Guaranteed by design and not 100% production tested.
AC ELECTRICAL CHARACTERISTICS—POWER SWITCH
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 2, Figure 2)
AC ELECTRICAL CHARACTERISTICS—I
2
C INTERFACE
(V
CC
or V
BAT
= +2.3V to +4.5V, T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at V
CC
= +3.3V, V
BAT
= +3.0V, and
T
A
= +25NC, unless otherwise noted.) (Notes 2, 7, Figure 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
V
CC Fall Time, VPFMAX to
V
PFMIN
tVCCF 300 Fs
VCC Rise Time, VPFMIN to
V
PFMAX
tVCCR 0 Fs
Recovery at Power-Up t
REC (Note 6) 250 300 ms
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency f
SCL 0 400 kHz
Bus Free Time Between STOP
and START Conditions
t
BUF 1.3 Fs
Hold Time (Repeated) START
Condition
t
HD:STA 0.6 Fs
Low Period of SCL t
LOW 1.3 Fs
High Period of SCL t
HIGH 0.6 Fs
Data Hold Time t
HD:DAT 0 0.9 Fs
Data Set-Up Time t
SU:DAT 100 ns
START Set-Up Time t
SU:STA 0.6 Fs
SDA and SCL Rise Time t
R (Note 8)
20 +
0.1C
B
300 ns
SDA and SCL Fall Time t
F (Note 8)
20 +
0.1C
B
300 ns
STOP Set-Up Time t
SU:STO 0.6 Fs
SDA, SCL Input Capacitance C
BIN (Note 9) 10 pF