Datasheet

DS3232M
±5ppm, I
2
C Real-Time Clock with SRAM
21Maxim Integrated
Slave Address Byte: Each slave on the I
2
C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit. The
device’s slave address is D0h and cannot be modi-
fied by the user. When the R/W bit is 0 (such as in
D0h), the master is indicating it writes data to the
slave. If R/W = 1 (D1h in this case), the master is
indicating it wants to read from the slave. If an incor-
rect slave address is written, the device assumes the
master is communicating with another I
2
C device and
ignore the communication until the next START condi-
tion is sent.
Memory Address: During an I
2
C write operation, the
master must transmit a memory address to identify
the memory location where the slave is to store the
data. The memory address is always the second byte
transmitted during a write operation following the
slave address byte.
I
2
C Communication
See Figure 10 for an I
2
C communication example.
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write
the byte of data, and generate a STOP condition.
Remember the master must read the slave’s acknowl-
edgment during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START con-
dition, writes the slave address byte (R/W = 0), writes
the starting memory address, writes multiple data
bytes, and generates a STOP condition.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the specified memory address
byte to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the slave,
the master generates a START condition, writes the
Figure 10. I
2
C Transactions
SLAVE
ADDRESS
START
START
1 1 0 1 0 0 0
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
R/W
MSB LSB MSB LSB MSB LSB
b7 b6 b5 b4 b3 b2 b1 b0
READ/
WRITE
REGISTER ADDRESS
b7 b6 b5 b4 b3 b2 b1 b0
DATA
STOP
SINGLE BYTE WRITE
-WRITE CONTROL REGISTER
TO 44h
MULTIBYTE WRITE
-WRITE DATE REGISTER
TO "02" AND MONTH
REGISTER TO "11"
SINGLE BYTE READ
-READ CONTROL REGISTER
MULTIBYTE READ
-READ ALARM 2 HOURS
AND DATE VALUES
START
REPEATED
START
D1h
MASTER
NACK
STOP1 1010000 00001110
0Eh
1 1010001
11010000 0 0001110
D0h 0Eh
STOP
VALUE
START 11010000 00000100
D0h 04h
DATA
MASTER
NACK
STOPVALUE
DATA
02h
44h
EXAMPLE I
2
C TRANSACTIONS
TYPICAL I
2
C WRITE TRANSACTION
01000100
00000010
D0h
A)
C)
B)
D)
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
REPEATED
START
D1h
MASTER
ACK
1 1010001 VALUE
DATA
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START 11010000 00001100
D0h 0Ch
SLAVE
ACK
SLAVE
ACK
STOP
11h
00010001
SLAVE
ACK