Datasheet

DS3232M
±5ppm, I
2
C Real-Time Clock with SRAM
19Maxim Integrated
Test Register (13h)
SRAM (14h–FFh)
Figure 8. Software Reset I/O Execution
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NAME:
SWRST 0 0 0 0 0 0 0
POR*:
0 0 0 0 0 0 0 0
*POR is defined as the first application of power to the device, either V
BAT
or V
CC
.
This register is used for factory test. Bits 6:0 are locked and always read as zeros. Writing to bit locations 6:0 has no affect on the
device. If the SWRST bit is set to Logic 1, the device immediately resets all internal logic and registers (except the SRAM) to their
factory-default POR state.
The device reset occurs during the normal acknowledge time slot following the receipt of the data byte carrying that SWRST
instruction; a NACK occurs due to the resetting action (see Figure 8). The I/O master should terminate the I/O string with a nor-
mal STOP instruction (on the 28th SCL clock). The SWRST bit is automatically cleared to logic 0.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
NAME:
D7 D6 D5 D4 D3 D2 D1 D0
POR*:
X X X X X X X X
*POR is defined as the first application of power to the device, either V
BAT
or V
CC
.
SDA 1111110 000 0000 00 00000001
SCL
SLAVE ADDRESS REGISTER ADDRESS
SLAVE ACKs NACK DURING SWRST
DATAR/W