Datasheet

DS3150
9 of 28
§ A third consecutive zero (0, 0, 0)
In E3 mode, HDB3 decoding is performed. RLCV is asserted during any RCLK cycle where the data on
RNRZ causes one of the following code violations:
§ A BPV immediately preceded by a valid pulse (B, V) or by a valid pulse and a zero (B, 0, V)
§ A BPV with the same polarity as the last BPV
§ A fourth consecutive zero (0, 0, 0, 0)
When RLCV is asserted to flag a BPV, the RNRZ pin outputs a 1. The state bit that tracks the polarity of
the last BPV is toggled on every BPV, whether part of a valid B3ZS/HDB3 codeword or not.
To support a glueless interface to a variety of neighboring components, the polarity of RCLK can be
inverted using the ICE input pin. See the ICE pin description in Table 2-A for details.
Receiver Jitter Tolerance. The receiver exceeds the input jitter tolerance requirements of all
applicable telecommunication standards in Table 1-A. See the graphs in Figure 1-3.
Receiver Jitter Transfer. The jitter transfer performance of the receiver, with and without the jitter
attenuator enabled, is shown in Figure 1-8.
Figure 1-3. Receiver Jitter Tolerance
E3 JITTER TOLERANCE
0.01
0.1
1
10
100
0.1 1 10 100 1000
FREQUENCY (kHz)
UI
P-P
G.823 and
ETSI 300 689
JA in R
x
JA disabled
DS3 JITTER TOLERANCE
0.01
0.1
1
10
100
0.01 0.1 1 10 100 1000
FREQUENCY (kHz)
UI
P-P
G
R-4
99
Cat
II
G.824
G
R-4
99
Cat
I
JA in Rx
JA disable
d
STS-1 JITTER TOLERANCE
0.01
0.1
1
10
100
0.01 0.1 1 10 100
1000
FREQUENCY (kHz)
UI
P-P
GR-253-CORE
JA in Rx
JA disabled
Note 1: All jitter tolerance curves are worst case over temperature,
voltage, cable length (0 to 900 feet), and RMON pin setting.
Note 2: The low-frequency plateau seen in most of the jitter tolerance
curves is not the actual performance of the DS3150 but rather
the limit of the measuring equipment (64 UI
P-P
). Actual jitter
tolerance in these low-frequency ranges is greater than or equal
to 64 UI
P-P
.
Note 3: Receiver jitter tolerance is not tested during production test.