Datasheet

DS3112
99 of 133
11 JTAG
The DS3112 device supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and
EXTEST. Optional public instructions included are HIGHZ, CLAMP, IDCODE (
Figure 11-1). The
DS3112 contains the following items that meet the requirements set by the IEEE 1149.1 Standard Test
Access Port and Boundary Scan Architecture:
 Test Access Port (TAP)
 TAP Controller
 Instruction Register
 Bypass Register
 Boundary Scan Register
 Device Identification Register
The Test Access Port has the necessary interface pins, namely JTCLK, JTRST, JTDI, JTDO, and JTMS.
Details on these pins can be found in Section
2.9. Details on the Boundary Scan Architecture and the Test
Access Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 11-1. JTAG Block Diagram
Boundary Scan
Register
Identification
Register
Bypass
Register
Instruction
Register
Test Access Port
Controller
Mux
Select
Tri-State
JTDI
10K
JTMS
10K
JTCLK
J
TRST
10K
JTDO