Datasheet

DS3112
95 of 133
Register Name:
IHSR
Register Description:
Interrupt Mask for HDLC Status Register
Register Address:
88h
Bit # 7 6 5 4 3 2 1 0
Name TUDR RPE RPS RHWM — TLWM — TEND
Default 0 0 0 0 — 0 — 0
Bit # 15 14 13 12 11 10 9 8
—
Name RABT — ROVR — — — —
Default 0 — 0 — — — — —
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Transmit Packet End (TEND).
0 = interrupt masked
1 = interrupt unmasked
Bit 2: Transmit FIFO Low Watermark (TLWM).
0 = interrupt masked
1 = interrupt unmasked
Bit 4: Receive FIFO High Watermark (RHWM).
0 = interrupt masked
Bit 13: Receive FIFO Overrun (ROVR).
1 = interrupt unmasked
Bit 5: Receive Packet Start (RPS).
0 = interrupt masked
1 = interrupt unmasked
Bit 6: Receive Packet End (RPE).
0 = interrupt masked
1 = interrupt unmasked
Bit 7: Transmit FIFO Underrun (TUDR).
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
Bit 15: Receive Abort Sequence Detected (RABT).
0 = interrupt masked
1 = interrupt unmasked