Datasheet

DS3112
84 of 133
Register Name:
BERTBC0
Register Description:
BERT 32-Bit Bit Counter (lower word)
Register Address:
78h
Bit # 7 6 5 4 3 2 1 0
Name
BBC7 BBC6 BBC5 BBC4 BBC3 BBC2 BBC1 BBC0
Default 0 0 0 0 0 0 0 0
Bit # 15 14 13 12 11 10 9 8
Name
BBC15 BBC14 BBC13 BBC12 BBC11 BBC10 BBC9 BBC8
Default 0 0 0 0 0 0 0 0
Register Name:
BERTBC1
Register Description:
BERT 32-Bit Bit Counter (upper word)
Register Address:
7Ah
Bit # 7 6 5 4 3 2 1 0
Name
BBC23 BBC22 BBC21 BBC20 BBC19 BBC18 BBC17 BBC16
Default 0 0 0 0 0 0 0 0
Bit # 15 14 13 12 11 10 9 8
Name
BBC31 BBC30 BBC29 BBC28 BBC27 BBC26 BBC25 BBC24
Default 0 0 0 0 0 0 0 0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 31: BERT 32-Bit Bit Counter (BBC0 to BBC31). This 32-bit counter will increment for each data bit
(i.e., clock received). This counter is not disabled when the receive BERT loses synchronization. This counter can
be cleared by toggling the LC control bit in BERTC0. This counter saturates and will not rollover. Upon saturation,
the BBCO status bit in the BERTEC0 register will be set. This error counter starts counting when the BERT goes
into receive synchronization (RLOS = 0 or SYNC = 1) and it will not stop counting when the BERT loses
synchronization. It is recommended that the host toggle the LC bit in BERTC0 register once the BERT has
synchronized and then toggle the LC bit again when the error-checking period is complete. If the device loses
synchronization during this period, then the counting results are suspect.