Datasheet

DS3112
76 of 133
Figure 7-1. T1LBSR1 and T1LBSR2 Status Bit Flow
LLB1
(T1LBSR1
Bit 0)
Internal T1
Loopback Command
Signal from
T2/E2 Framer
OR
Mask
T1LB
(IMSR Bit 8)
INT*
Hardware
Signal
T1LB
Status Bit
(MSR Bit 8)
LLB2
(T1LBSR1
Bit 1)
Internal T1
Loopback Command
Signal from
T2/E2 Framer
LLB28
(T1LBSR2
Bit 11)
Internal T1
Loopback Command
Signal from
T2/E2 Framer
7.7 T1/E1 Drop and Insert Control Register Description
Register Name:
T1E1SDP
Register Description:
T1/E1 Select Register for Receive Drop Ports A and B
Register Address:
60h
Bit # 7 6 5 4 3 2 1 0
Name — — — DPAS4 DPAS3 DPAS2 DPAS1 DPAS0
Default — — — 0 0 0 0 0
Bit # 15 14 13 12 11 10 9 8
Name — — — DPBS4 DPBS3 DPBS2 DPBS1 DPBS0
Default — — — 0 0 0 0 0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 4: T1/E1 Drop Port A Select Bits (DPAS0 to DPAS4).
Bits 8 to 12: T1/E1 Drop Port B Select Bits (DPBS0 to DPBS4).
These bits select which of the 28 T1 ports or 16 E1 ports (if any) should be output at either Drop Port A or Drop
Port B. If no port is selected, the LRDATA, LRCLKA, LRDATB, and LRCLKB output pins will be forced low.
DPxS4:0
00000 No Port 01000 Port 8 10000 Port 16 11000 Port 24
00001 Port 1 01001 Port 9 10001 Port 17 11001 Port 25
00010 Port 2 01010 Port 10 10010 Port 18 11010 Port 26
00011 Port 3 01011 Port 11 10011 Port 19 11011 Port 27
00100 Port 4 01100 Port 12 10100 Port 20 11100 Port 28
00101 Port 5 01101 Port 13 10101 Port 21 11101 No Port
00110 Port 6 01110 Port 14 10110 Port 22 11110 No Port
00111 Port 7 01111 Port 15 10111 Port 23 11111 No Port