Datasheet

DS3112
60 of 133
Register Name:
FECR
Register Description:
Frame Error Count Register
Register Address:
24h
Bit # 7 6 5 4 3 2 1 0
Name
FE7 FE6 FE5 FE4 FE3 FE2 FE1 FE0
Default — — — — — — — —
Bit # 15 14 13 12 11 10 9 8
Name FE15
FE14 FE13 FE12 FE11 FE10 FE9 FE8
Default — — — — — — — —
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: 16-Bit Framing Bit Error Counter (FE0 to FE15). These bits report either the number of Loss Of
Frame (LOF) occurrences or the number of framing bit errors received. The FECR is configured via the host by the
Frame Error Counting Control Bits (FECC0 and FECC1) in the T3E3 Control Register (Section
5.2). The possible
configurations are shown below.
FECC1 FECC0
FRAME ERROR COUNT REGISTER (FECR)
CONFIGURATION
0 0
T3 Mode: Count Loss Of Frame (LOF) Occurrences
E3 Mode: Count Loss Of Frame (LOF) Occurrences
0 1
T3 Mode: Count both F Bit and M Bit Errors
E3 Mode: Count Bit Errors in the FAS Word
1 0
T3 Mode: Count Only F Bit Errors
E3 Mode: Count Word Errors in the FAS Word
1 1
T3 Mode: Count only M Bit Errors
E3 Mode: Illegal State
When the FECR is configured to count LOF occurrences, the FECR increments by one each time the device loses
receive synchronization. When the FECR is configured to count framing bit errors, it can be configured via the
ECC control bit in the T3/E3 Control Register (Section
5.2) to either continue counting frame bit errors during a
LOF or not.
Register Name:
PCR
Register Description:
T3 Parity Bit Error Count Register
Register Address:
26h
Bit # 7 6 5 4 3 2 1 0
Name
PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
Default
— — — — — — — —
Bit # 15 14 13 12 11 10 9 8
Name PE15
PE14 PE13 PE12 PE11 PE10 PE9 PE8
Default
— — — — — — — —
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15:16-Bit T3 Parity Bit Error Counter (PE0 to PE15). These bits report the number of T3 parity bit
errors. In the E3 mode, this counter is meaningless and should be ignored. A parity bit error is defined as an
occurrence when the two parity bits do not match one another or when the two Parity Bits do not match the parity
calculation made on the information bits. Via the ECC control bit in the T3/E3 Control Register (Section
5.2), the
PCR can be configured to either continue counting parity bit errors during a LOF or not.