Datasheet

DS3112
54 of 133
Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR)
register is set to a one.
Bit 6: Receive T3/E3 Start Of Frame (RSOF). This latched read-only event status bit will be set to a one on each
T3/E3 receive frame boundary. This bit is a software version of the FRSOF hardware signal and it will be cleared
when read. The setting of this bit can cause a hardware interrupt to occur if the RSOF bit in the Interrupt Mask for
T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is
set to a one.
Figure 5-1. T3E3SR Status Bit Flow
OR
Mask
T3E3SR
(IMSR Bit 9)
INT*
Hardware
Signal
T3E3SR
Status Bit
(MSR Bit 9)
A
larm Latch
Receive LOS
Signal from
T3/E3 Framer
LOS
(T3E3SR Bit 0)
Mask
LOS (IT3E3SR Bit 0)
Change in State Detect
A
larm Latch
Receive LOF
Signal from
T3/E3 Framer
LOF
(T3E3SR Bit 1)
Mask
LOF (IT3E3SR Bit 1)
Change in State Detect
A
larm Latch
Receive AIS
Signal from
T3/E3 Framer
A
IS
(T3E3SR Bit 2)
Mask
A
IS (IT3E3SR Bit 2)
Change in State Detect
A
larm Latch
Receive RAI
Signal from
T3/E3 Framer
RAI
(T3E3SR Bit 3)
Mask
RAI (IT3E3SR Bit 3)
Change in State Detect
A
larm Latch
Receive Idle
Signal from
T3/E3 Framer
T3IDLE
(T3E3SR Bit 4)
Mask
T3IDLE (IT3E3SR Bit 4)
Change in State Detect
Event Latch
Receive Start
Of Frame
Signal from
T3/E3 Framer
TSOF
(T3E3SR Bit 5)
Mask
TSOF (IT3E3SR Bit 5)
Event Latch
Transmit Start
Of Frame
Signal from
T3/E3 Framer
RSOF
(T3E3SR Bit 6)
Mask
RSOF (IT3E3SR Bit 6)
Event Latch
Event Latch
Event Latch
Event Latch
Event Latch
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE T3E3SR REGISTER IS READ.