Datasheet

DS3112
31 of 133
3 MEMORY MAP
Table 3-1. Memory Map
ADDRESS ACRONYM R/W REGISTER NAME SECTION
00 MRID R/W Master Reset and ID Register 4.1
02 MC1 R/W Master Configuration Register 1 4.2
04 MC2 R/W Master Configuration Register 2 4.2
06 MC3 R/W Master Configuration Register 3 4.2
08 MSR R Master Status Register 4.3
0A IMSR R/W Interrupt Mask Register for MSR 4.3
0C TEST R/W Test Register 4.4
10 T3E3CR R/W T3/E3 Control Register 5.2
12 T3E3SR R T3/E3 Status Register 5.3
14 IT3E3SR R/W Interrupt Mask for T3E3SR 5.3
16 T3E3INFO R T3/E3 Information Register 5.3
18 T3E3EIC R/W T3/E3 Error Insert Control Register 5.3
20 BPVCR R T3/E3 Bipolar Violation (BPV) Count Register 5.4
22 EXZCR R T3/E3 Excessive Zero (EXZ) Count Register 5.4
24 FECR R T3/E3 Frame Error Count Register 5.4
26 PCR R T3 Parity Bit Error Count Register 5.4
28 CPCR R T3 C-Bit Parity Error Count Register 5.4
2A FEBECR R T3 Far End Block Error or E3 RAI Count Register 5.4
30 T2E2CR1 R/W T2/E2 Control Register 1 6.2
32 T2E2CR2 R/W T2/E2 Control Register 2 6.2
34 T2E2SR1 R/W T2/E2 Status Register 1 6.4
36 T2E2SR2 R/W T2/E2 Status Register 2 6.4
40 T1E1RAIS1 R/W T1/E1 Receive Path AIS Generation Control Register 1 6.4
42 T1E1RAIS2 R/W T1/E1 Receive Path AIS Generation Control Register 2
6.4
44 T1E1TAIS1 R/W T1/E1 Transmit Path AIS Generation Control Register 1
6.4
46 T1E1TAIS2 R/W T1/E1 Transmit Path AIS Generation Control Register 2
6.4
50 T1E1LLB1 R/W T1/E1 Line Loopback Control Register 1 7.1
52 T1E1LLB2 R/W T1/E1 Line Loopback Control Register 2 7.1
54 T1E1DLB1 R/W T1/E1 Diagnostic Loopback Control Register 1 7.2
56 T1E1DLB2 R/W T1/E1 Diagnostic Loopback Control Register 2 7.2
58 T1LBCR1 R/W T1 Line Loopback Command Register 1 7.3
5A T1LBCR2 R/W T1 Line Loopback Command Register 2 7.3
5C T1LBSR1 R T1 Line Loopback Status Register 1 7.6
5E T1LBSR2 R T1 Line Loopback Status Register 2 7.6
60 T1E1SDP R/W T1/E1 Select Register for Receive Drop Ports A and B 7.4
62 T1E1SIP R/W T1/E1 Select Register for Transmit Drop Ports A and B 7.4
6E BERTMC R/W BERT Mux Control Register 8.1
70 BERTC0 R/W BERT Control 0 8.1
72 BERTC1 R/W BERT Control 1 8.1
74 BERTRP0 R/W BERT Repetitive Pattern Set 0 (lower word) 8.1
76 BERTRP1 R/W BERT Repetitive Pattern Set 1 (upper word)
8.1
78 BERTBC0 R BERT Bit Counter 0 (lower word)
8.1
7A BERTBC1 R BERT Bit Counter 1 (upper word)
8.1
7C BERTEC0 R BERT Error Counter 0 (lower word)
8.1
7E BERTEC1 R BERT Error Counter 1 (upper word)
8.1
80 HCR R/W HDLC Control Register 9.1