Datasheet

DS3112
TABLE OF CONTENTS
1 DETAILED DESCRIPTION 7
1.1 APPLICABLE STANDARDS ..............................................................................................................8
1.2 MAIN DS3112 TEMPE FEATURES................................................................................................9
1.2.1 General Features ................................................................................................................................... 9
1.2.2 T3/E3 Framer......................................................................................................................................... 9
1.2.3 T2/E2 Framer......................................................................................................................................... 9
1.2.4 HDLC Controller..................................................................................................................................... 9
1.2.5 FEAC Controller..................................................................................................................................... 9
1.2.6 BERT.................................................................................................................................................... 10
1.2.7 Diagnostics........................................................................................................................................... 10
1.2.8 Control Port.......................................................................................................................................... 10
1.2.9 Packaging and Power.......................................................................................................................... 10
2 PIN DESCRIPTION 14
2.2 CPU BUS SIGNAL DESCRIPTION .................................................................................................19
2.3 T3/E3 RECEIVE FRAMER SIGNAL DESCRIPTION...........................................................................21
2.4 T3/E3 TRANSMIT FORMATTER SIGNAL DESCRIPTION ...................................................................23
2.5 LOW-SPEED (T1 OR E1) RECEIVE PORT SIGNAL DESCRIPTION ....................................................25
2.6 LOW-SPEED (T1 OR E1) TRANSMIT PORT SIGNAL DESCRIPTION ..................................................26
2.7 HIGH-SPEED (T3 OR E3) RECEIVE PORT SIGNAL DESCRIPTION ...................................................28
2.8 HIGH-SPEED (T3 OR E3) TRANSMIT PORT SIGNAL DESCRIPTION .................................................28
2.9 JTAG SIGNAL DESCRIPTION .......................................................................................................29
2.10 SUPPLY, TEST, RESET, AND MODE SIGNAL DESCRIPTION............................................................29
3 MEMORY MAP 31
4 MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT 33
4.1 MASTER RESET AND ID REGISTER DESCRIPTION.........................................................................33
4.2 MASTER CONFIGURATION REGISTERS DESCRIPTION ...................................................................34
4.3 MASTER STATUS AND INTERRUPT REGISTER DESCRIPTION..........................................................38
4.3.1 Status Registers................................................................................................................................... 38
4.3.2 MSR ..................................................................................................................................................... 39
4.4 TEST REGISTER DESCRIPTION ....................................................................................................47
5 T3/E3 FRAMER 48
5.1 T3/E3 LINE LOOPBACK ...............................................................................................................48
5.2 T3/E3 DIAGNOSTIC LOOPBACK ...................................................................................................48
5.3 T3/E3 PAYLOAD LOOPBACK........................................................................................................48
5.4 T3/E3 FRAMER CONTROL REGISTER DESCRIPTION .....................................................................49
5.5 T3/E3 FRAMER STATUS AND INTERRUPT REGISTER DESCRIPTION ...............................................53
5.6 T3/E3 PERFORMANCE ERROR COUNTERS ..................................................................................59
6 M13/E13/G.747 MULTIPLEXER AND T2/E2/G.747 FRAME 62
6.1 T1/E1 AIS GENERATION.............................................................................................................62
6.2 T2/E2/G.747 FRAMER CONTROL REGISTER DESCRIPTION ..........................................................62
6.3 T2/E2/G.747 FRAMER STATUS AND INTERRUPT REGISTER DESCRIPTION ....................................64
6.4 T1/E1 AIS GENERATION CONTROL REGISTER DESCRIPTION .......................................................68
7 T1/E1 LOOPBACK AND DROP AND INSERT FUNCTIONALITY 70
7.1 T1/E1 LINE LOOPBACK ...............................................................................................................70
7.2 T1/E1 DIAGNOSTIC LOOPBACK ...................................................................................................70
7.3 T1 LINE LOOPBACK COMMAND....................................................................................................70
7.4 T1/E1 DROP AND INSERT............................................................................................................70
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7.5 T1/E1 LOOPBACK CONTROL REGISTER DESCRIPTION .................................................................71