Datasheet

DS3112
14 of 133
2 PIN DESCRIPTION
This section describes the input and output signals on the DS3112. Signal names follow a convention that
is shown in
Table 2-1. Table 2-2 lists all the signals, their signal type, description, and pin location.
Table 2-1. Pin Naming Convention
FIRST
LETTERS
SIGNAL CATEGORY SECTION
C CPU/Host Control Access Port 2.2
FR T3/E3 Receive Framer 2.3
FT T3/E3 Transmit Formatter 2.4
LR Low-Speed (T1 or E1) Receive Port 2.5
LT Low-Speed (T1 or E1) Transmit Port 2.6
HR High-Speed (T3 or E3) Receive Port 2.7
HT High-Speed (T3 or E3) Transmit Port 2.8
J JTAG Test Port 2.9
Table 2-2. Pin Description
PIN NAME TYPE FUNCTION
C7 CALE I CPU Bus Address Latch Enable
H3 CA0 I CPU Bus Address Bit 0 (LSB)
H2 CA1 I CPU Bus Address Bit 1
H1 CA2 I CPU Bus Address Bit 2
J4 CA3 I CPU Bus Address Bit 3
J3 CA4 I CPU Bus Address Bit 4
J2 CA5 I CPU Bus Address Bit 5
J1 CA6 I CPU Bus Address Bit 6
K2 CA7 I CPU Bus Address Bit 7 (MSB)
C4
CCS
I CPU Bus Chip Select (Active Low)
C2 CD0 I/O CPU Bus Data Bit 0 (LSB)
D2 CD1 I/O CPU Bus Data Bit 1
D3 CD2 I/O CPU Bus Data Bit 2
E4 CD3 I/O CPU Bus Data Bit 3
C1 CD4 I/O CPU Bus Data Bit 4
D1 CD5 I/O CPU Bus Data Bit 5
E3 CD6 I/O CPU Bus Data Bit 6
E2 CD7 I/O CPU Bus Data Bit 7
E1 CD8 I/O CPU Bus Data Bit 8
F3 CD9 I/O CPU Bus Data Bit 9
G4 CD10 I/O CPU Bus Data Bit 10
F2 CD11 I/O CPU Bus Data Bit 11
F1 CD12 I/O CPU Bus Data Bit 12
G3 CD13 I/O CPU Bus Data Bit 13
G2 CD14 I/O CPU Bus Data Bit 14
G1 CD15 I/O CPU Bus Data Bit 15 (MSB)
B3 CIM I CPU Bus Intel/Motorola Bus Select, 0 = Intel, 1 = Motorola
A2
CINT
O CPU Bus Interrupt
B2 CMS I CPU Bus Mode Select, 0 = 16 Bit, 1 = 8 Bit Mode