Datasheet

DS3112
12 of 133
Figure 1-2. DS3112 Framer and Multiplexer Block Diagram (E3 Mode)
AIS Gen.
FIFO
AIS Gen.
FIFO
AIS Gen.
FIFO
AIS Gen.
FIFO
1 of 4
AIS Gen.
FIFO
1 of 4
To BERT
1 of 16
Sn Bit Insertion
FAS & RAI Generation
HDB3 Coder / Unipolar Coder & BPV Insertion
FAS / RAI / Sn / AIS Generation
E2
For-
matter
4 to 1
Mux
4 to 1
Mux
C Bit Generation
& Bit Stuffing Control
C Bit Generation & Bit Stuffing Control
E3
Formatter
Sync
Control
Signal
Inversion
Control
FTCLK
FTD
FTDEN
FTSOF
mux
Signal Inversion & Force Data Control / AIS Generation
Sn Bit Extraction
Alarm & Error Detection
E3 Framer
HDB3 Decoder / Unipolar Decoder & BPV Detector
E3
Framer
Signal Inversion
AIS Gen.
FIFO
To BERT
AIS Gen.
FIFO
To BERT
AIS Gen.
FIFO
To BERT
C Bit Decoding & Bit Destuffing Control
E2 Framer
Alarm & Sn Bit Detection
E2
Framer
1 to 4
Demux
1 to 4
Demux
C Bit Decoding & Bit Destuffing Control
Error
Counters
E3 Line Loopback
E3 Diagnostic Loopback
E3 Payload Loopback
E1 Line Loopback
E1 Diagnostic Loopback
HDLC Controller
with 256 Byte
Buffer
FEAC Controller
Signal
Inversion
Control
1
2
4
4
1
2
Signal Inversion Control
Signal Inversion Control
LTCLK
LTDAT
LTCLK
LTDAT
LTCLK
LTDAT
LTCLK
LTDAT
LRCLK
LRDAT
LRCLK
LRDAT
LRCLK
LRDAT
LRCLK
LRDAT
LRCCLK
FRSOF
FRCLK
FRD
FRDEN
HRPOS
HRNEGHRCLK
HTPOS
HTNEG
HTCLK
Receive
BERT
BERT Mux
Transmit
BERT
BERT Mux
FRLOF
FRLOS
BERT Insert
BERT Insert
BERT Insert
BERT Insert
Loss Of Transmit Clock
HRCLK
LTCCLK
LTDATA
LTCLKA
LTDATB
LTCLKB
LRCLKA
LRCLKB
LRDATA
LRDATB
from
other
ports
from
other
ports
Diagnostic Error Insertion
FRMECU
Transmit
Receive
JTAG
Test
Block
JTMS
JTDO
JTDI
JTCLK
JTRST*
FTMEI
E1 Loop Timed Mode
3
3
CPU Interface & Global Configuration
(Routed to All Blocks)
T3E3MS
(tied high)
G747E
(tied low)
CD0 to
CD15
CA0 to
CA7
CWR*
(CR/W*)
CRD*
(CDS*)
CCS* CIM CINT* CMS TEST RST*CALE