Datasheet

DS3112
118 of 133
Figure 13-10. Motorola Read Cycle (Multiplexed)
Data Valid
CD[15:0]
C
R/W
C
CS
C
DS
t1
t2 t3
t4
t5
t10
A
ddress
Valid
CA[7:0]
CALE
t11
t12
t13
t14
t14
NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS, WHICHEVER OCCURS FIRST.
Figure 13-11. Motorola Write Cycle (Multiplexed)
CD[15:0]
C
R/W
C
CS
C
DS
t1
t2
t6
t4
t7 t8
t10
A
ddress
Valid
CA[7:0]
CALE
t11
t12
t13
t14
t14
NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS, WHICHEVER OCCURS FIRST.