
DS3112
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Figure 13-6. Motorola Read Cycle (Nonmultiplexed)
ddress Valid
Data Valid
CA[7:0]
CD[15:0]
R/W
CS
DS
t1
t2 t3 t4
t5
t9
t10
Figure 13-7. Motorola Write Cycle (Nonmultiplexed)
ddress ValidCA[7:0]
CD[15:0]
R/
CS
DS
t1
t2 t6 t4
t7 t8
t9
t10