Datasheet

DS3112
115 of 133
Figure 13-4. Intel Read Cycle (Nonmultiplexed)
Figure 13-5. Intel Write Cycle (Nonmultiplexed)
A
ddress Valid
Data Valid
CA[7:0]
CD[15:0]
C
WR
C
CS
C
RD
t1
t2 t3 t4
t5
t9
t10
A
ddress ValidCA[7:0]
CD[15:0]
C
RD
C
CS
C
WR
t1
t2 t6 t4
t7 t8
t9
t10