Datasheet

DS3112
113 of 133
Figure 13-
Table 13-3. AC Characteristics–Framer (T3 and E3) Ports
(V
DD
= 3.3V ±5%, T
A
= 0°C to +70°C for DS3112; T
A
= -40°C to +85°C for DS3112N.)
(See 3.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
22.4 ns 1, 3
FRCLK/FTCLK Clock Period t1
29.1 ns 2, 3
FTCLK Clock Low Time t2 9 ns
FTCLK Clock High Time t3 9 ns
FTD/FTSOF Setup Time to the
Rising Edge or Falling Edge of
FTCLK
t4 3 ns 4
FTD/FTSOF Hold Time from the
Rising Edge or Falling Edge of
FTCLK
t5 3 ns 4
Delay from the Rising Edge or
Falling Edge of FRCLK/FTCLK to
Data Valid on FRDEN/FRD/
FRSOF/FTDEN/FTSOF
t6 3 10 ns 5
NOTES:
1) T3 mode.
2) E3 mode.
3) FRCLK is a buffered version of either FTCLK or HRCLK and, as such, the duty cycle of FRCLK is
determined by the source clock.
4) FTSOF is configured to be an input.
5) FTSOF is configured to be an output.
6) In normal mode, FTD (and FTSOF if it is configured as an input) is sampled on the rising edge of FTCLK and
FRDEN, FRD, FRSOF, and FTDEN (and FTSOF if it is configured as an output) are updated on the rising
edge of FRCLK or FTCLK.
7) In inverted mode, FTD (and FTSOF if it is configured as an input) is sampled on the falling edge of FTCLK
and FRDEN, FRD, FRSOF, and FTDEN (and FTSOF if it is configured as an output) are updated on the
falling edge of FRCLK or FTCLK.
Figure 13-3. Framer (T3 and E3) Port AC Timing Diagram
FRCLK / FTCLK
Normal Mode
FTD / FTSOF
FRD / FRDEN /
FRSOF / FTSOF /
FTDEN
t4 t5
t6
t1
t2 t3
FRCLK / FTCLK
Inverted Mode
ls_ac