Datasheet

DS3112
11 of 133
Figure 1-1. DS3112 Framer and Multiplexer Block Diagram (T3 Mode)
AIS Gen.
FIFO
AIS Gen.
FIFO
AIS Gen.
FIFO
AIS Gen.
FIFO
1 of 7
AIS Gen.
FIFO
1 of 7
To BERT
CPU Interface & Global Configuration
(Routed to All Blocks)
1 of 28
C Parity Mode [includes HDLC Data Link, FEAC, FEBE, CP, and Application ID Insertion]
M / F / P / X Bit Generation
B3ZS Coder / Unipolar Coder & BPV Insertion
M / F / X Bit & AIS Generation
T2
For-
matter
7 to 1
Mux
4 to 1
Mux
C Bit Generation (M13 Mode Only)
& Bit Stuffing Control
C Bit Generation & Bit Stuffing Control
T3
Formatter
Sync
Control
Signal
Inversion
Control
FTCLK
FTD
FTDEN
FTSOF
mux
Signal Inversion & Force Data Control / AIS Generation
C Parity Mode [extracts HDLC Data Link, FEAC, FEBE, CP, and Application ID bit]
Alarm & Error Detection
T3 Framer
B3ZS Decoder / Unipolar Decoder & BPV Detector
T3
Framer
Signal Inversion
AIS Gen.
FIFO
To BERT
AIS Gen.
FIFO
To BERT
AIS Gen.
FIFO
To BERT
C Bit Decoding & Bit Destuffing Control
T2 Framer
Alarm & Loopback Detection
T2
Framer
1 to 4
Demux
1 to 7
Demux
C Bit Decoding (M13 Mode Only)
& Bit Destuffing Control
Error
Counters
T3 Line Loopback
T3 Diagnostic Loopback
T3 Payload Loopback
T1 Line Loopback
T1 Diagnostic Loopback
HDLC Controller
with 256 Byte
Buffer
FEAC Controller
Signal
Inversion
Control
1
2
7
7
1
2
Signal Inversion Control
Signal Inversion Control
LTCLK
LTDAT
LTCLK
LTDAT
LTCLK
LTDAT
LTCLK
LTDAT
LRCLK
LRDAT
LRCLK
LRDAT
LRCLK
LRDAT
LRCLK
LRDAT
LRCCLK
FRSOF
FRCLK
FRD
FRDEN
HRPOS
HRNEGHRCLK
HTPOS
HTNEG
HTCLK
Receive
BERT
BERT Mux
Transmit
BERT
BERT Mux
FRLOF
FRLOS
BERT Insert
BERT Insert
BERT Insert
BERT Insert
Loss Of Transmit Clock
HRCLK
LTCCLK
LTDATA
LTCLKA
LTDATB
LTCLKB
LRCLKA
LRCLKB
LRDATA
LRDATB
from
other
ports
from
other
ports
Diagnostic Error Insertion
FRMECU
Transmit
Receive
T3E3MS
(tied low)
JTAG
Test
Block
JTMS
JTDO
JTDI
JTCLK
JTRST*
FTMEI
T1 Loop Timed Mode
G747E
(tied low)
CD0 to
CD15
CA0 to
CA7
CWR*
(CR/W*)
CRD*
(CDS*)
CCS* CIM CINT* CMS TEST RST*CALE