Datasheet

DS3112
104 of 133
11.3.3
Table 11-2
11.2.6 CLAMP
All digital outputs will output data from the boundary scan parallel output while connecting the Bypass
Register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
11.3 Test Registers
IEEE 1149.1 requires a minimum of two test registers, the bypass register and the boundary scan register.
An optional test register, the Identification register, has been included in the DS3112 design. It is used in
conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
11.3.1 Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGH-Z
instructions that provides a short path between JTDI and JTDO.
11.3.2 Identification Register
The Identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is 196 bits in length.
shows all the cell bit locations and definitions.
Table 11-2. Boundary Scan Control Bits
BIT SYMBOL PIN
I/O OR CONTROL BIT
DESCRIPTION
0 OUT_ENB Control bit
0 = outputs are active
1 = outputs are tri-state (“z”)
1 TEST C3 I
2 CINT_ENB_N Control bit
0 = CINT is a zero (“0”)
1 = CINT is tri-state (“z”)
3 CINT_OUT A2 O (open drain)
4 CINT_IN A2 I
5 CMS B2 I
6 CIM B3 I
7
CCS
C4 I
8
CRD
D5 I
9
CWR
A3 I
10 T3E3MS B4 I
11
RST
C5 I
12 G.747E B6 I
13 CALE C7 I
14 FRMECU A7 I
15 FRLOF C8 O
16 FRLOS B8 O
17 FRSOF A8 O
18 FRDEN C9 O
19 FRD B9 O
20 FRCLK A9 O
21 FTDEN C10 O