Information

ManualsBrandsMAXIM INTEGRATED ManualsDev KitsStarter kit

DS28E25

DeepCover Secure Authenticator with

1-Wire SHA-256 and 4Kb User EEPROM

3Maxim Integrated

ELECTRICAL CHARACTERISTICS (continued)

= -40NC to +85NC, unless otherwise noted.) (Note 1)

Note 1: Limits are 100% production tested at T

= +25°C and/or T

= +85°C. Limits over the operating temperature range and

relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.

Note 2:

System requirement.

Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery

times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.

Note 4:

Typical value represents the internal parasite capacitance when V

PUP

is first applied. Once the parasite capacitance is

charged, it does not affect normal communication.

Note 5:

Guaranteed by design and/or characterization only; not production tested.

Note 6: V

, V

, and V

are a function of the internal supply voltage, which is a function of V

PUP

, R

PUP

, 1-Wire timing, and

capacitive loading on IO. Lower V

PUP

, higher R

PUP

, shorter t

REC

, and heavier capacitive loading all lead to lower values

of V

, V

, and V

Note 7:

Voltage below which, during a falling edge on IO, a logic-zero is detected.

Note 8: The voltage on IO must be less than or equal to V

ILMAX

at all times when the master is driving IO to a logic-zero level.

Note 9: Voltage above which, during a rising edge on IO, a logic-one is detected.

Note 10: After V

is crossed during a rising edge on IO, the voltage on IO must drop by at least V

to be detected as logic-zero.

Note 11:

The I-V characteristic is linear for voltages less than 1V.

Note 12: Applies to a single device attached to a 1-Wire line.

Note 13: Defines maximum possible bit rate. Equal to 1/(t

W0LMIN

+ t

RECMIN

Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired.

Note 15: Interval after t

RSTL

during which a bus master can read a logic 0 on IO if there is a DS28E25 present. The power-up pres-

ence detect pulse could be outside this interval, but will be complete within 2ms after power-up.

Note 16:

ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V

to V

. The actual

maximum duration for the master to pull the line low is t

W1LMAX

+ t

- ε and t

W0LMAX

+ t

- ε, respectively.

Note 17: d in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from V

to the input-high

threshold of the bus master. The actual maximum duration for the master to pull the line low is t

RLMAX

+ t

Note 18:

Current drawn from IO during the EEPROM programming interval or SHA-256 computation. The pullup circuit on IO during

the programming interval or SHA-256 computation should be such that the voltage at IO is greater than or equal to 2.0V.

Note 19: Refer to the full data sheet.

Note 20: Refer to the full data sheet.

Note 21: Write-cycle endurance is tested in compliance with JESD47G.

Note 22: Not 100% production tested; guaranteed by reliability monitor sampling.

Note 23: Data retention is tested in compliance with JESD47G.

Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the

data sheet limit at operating temperature range is established by reliability testing.

Note 25: EEPROM writes can become nonfunctional after the data retention time is exceeded. Long-term storage at elevated tem-

peratures is not recommended.

Note 26: Refer to the full data sheet.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SHA-256 ENGINE

Computation Current I

CSHA

Refer to the full data sheet.

Computation Time t

CSHA

ABRIDGED DATA SHEET