Datasheet

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GENERAL DESCRIPTION

The DS28E04-100 is a 4096-bit, 1-Wire

EEPROM

chip with seven address inputs. The address inputs

are directly mapped into the 1-Wire 64-bit Device ID

Number to easily enable the host system to identify

the physical location or functional association of the

DS28E04-100 in a multidevice 1-Wire network en-

vironment. The 4096-bit EEPROM array is configured

as 16 pages of 32 bytes with a 32 byte scratchpad to

perform write operations. EEPROM memory pages

can be individually write protected or put in EPROM-

emulation mode, where bits can only be changed

from a 1 to a 0 state. In addition to the memory, the

DS28E04-100 has two general-purpose I/O ports that

can be used for input or to generate level and/or

pulse outputs. Activity registers also capture port

activity for state change monitoring. The DS28E04-

100 communicates over the single-contact 1-Wire

bus. The communication follows the standard Maxim

1-Wire protocol.

APPLICATIONS

Autoconfiguration of Modular Systems such as

Central-Office Switches, Cellular Base Stations,

Access Products, Optical Network Units, and

PBXs

Accessory/PCB Identification

TYPICAL OPERATING CIRCUIT

PX.Y

µC

PUP

IO V

POL

GND

DS28E04 #1

IO V

POL

GND

DS28E04 #7

RST1 RST0

LED

FEATURES

• 4096 bits of EEPROM Memory Partitioned into

16 Pages of 256 Bits

• Seven Address Inputs for Physical Location

Configuration

• Two General-Purpose PIO Pins with Pulse-

Generation Capability

 Individual Memory Pages can be Permanently

Write-Protected or put in OTP EPROM-

Emulation Mode (“Write to 0”)

 Communicates to Host with a Single Digital

Signal at 15.3kbps or 111kbps Using 1-Wire

Protocol

 Parasitic or V

Powered

 Conditional Search Based on PIO Status or PIO

Activity

 Switchpoint Hysteresis and Filtering to Optimize

Performance in the Presence of Noise

 Reads and Writes Over a Wide 2.8V to 5.25V

Voltage Range from -40°C to +85°C

 16-Pin, 150-mil SO Package

ORDERING INFORMATION

PART

TEMP RANGE

PIN-PACKAGE

DS28E04S-100+

-40°C to +85°C

16 SO

DS28E04S-100+T -40°C to +85°C

16 SO

(2.5k pieces)

+ Indicates lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

PIN CONFIGURATION

SO (150 mils)

Commands, Registers, and Modes are capitalized for

clarity.

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

DS28E04-100

4096-Bit Addressable 1-

Wire EEPROM with PIO

19-6134; Rev 12/11

Summary of content (37 pages)

PAGE 1
9-6134; Rev 12/11 DS28E04-100 4096-Bit Addressable 1-Wire EEPROM with PIO GENERAL DESCRIPTION FEATURES ® • The DS28E04-100 is a 4096-bit, 1-Wire EEPROM chip with seven address inputs. The address inputs are directly mapped into the 1-Wire 64-bit Device ID Number to easily enable the host system to identify the physical location or functional association of the DS28E04-100 in a multidevice 1-Wire network environment.
PAGE 2
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO ABSOLUTE MAXIMUM RATINGS All Pins: Voltage to GND All Pins: Sink Current Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature (soldering, 10s) Soldering Temperature (reflow) -0.5V, +6V 20mA -40°C to +85°C +150°C -55°C to +125°C +300°C +260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
PAGE 3
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO PARAMETER SYMBOL CONDITIONS Standard speed Time Slot Duration tSLOT (Note 1) Overdrive speed IO PIN, 1-Wire RESET, PRESENCE DETECT CYCLE Standard speed, VPUP > 4.5V Standard speed (Note 17) Reset Low Time (Note 1) tRSTL Overdrive speed, VPUP > 4.5V Overdrive speed (Note 17) Standard speed Presence-Detect High tPDH Time Overdrive speed (Note 17) Standard speed, VPUP > 4.
PAGE 4
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Note 19: Note 20: Note 21: Note 22: Note 23: Note 24: ε in Figure 16 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to V TH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε respectively. δ in Figure 16 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high threshold of the bus master.
PAGE 5
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS28E04-100. The DS28E04-100 has five main data components: 1) 64-bit device ID number, 2) 32-byte scratchpad, 3) sixteen 32-byte pages of EEPROM, 4) Special Function Register, and 5) PIO Control Registers. The hierarchical structure of the 1-Wire protocol is shown in Figure 2.
PAGE 6
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 2. Hierarchical Structure for 1-Wire Protocol DS28E04-100 Available Commands: Data Field Affected: 1-Wire ROM Function Commands (see Figure 14) Read ROM Match ROM Search ROM Conditional Search ROM Skip ROM Resume Overdrive Skip Overdrive Match Device ID, RC-Flag Device ID, RC-Flag Device ID, RC-Flag Device ID, RC-Flag, PIO Status, cond.
PAGE 7
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 4. 1-Wire CRC Generator 8 5 4 Polynomial = X + X + X + 1 st nd 1 STAGE X 0 rd 2 STAGE X 1 th 3 STAGE X 2 X 3 th th 4 STAGE X 4 th 6 STAGE 5 STAGE X 5 th 7 STAGE X 6 8 STAGE X 7 X 8 INPUT DATA MEMORY The DS28E04-100 EEPROM array consists of 17 pages of 32 bytes each, starting at address 0000h and ending at address 021Fh. All memory addresses in this range have unrestricted read access.
PAGE 8
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 5. Memory Map Address locations 0000h to 021Fh are nonvolatile. Address locations 0220h to 0225 are volatile.
PAGE 9
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO PIO-RELATED REGISTERS Figure 6 shows the simplified logic diagram of a PIO channel. The registers related to the PIO pins are located in the address range 0220h to 0225h. All these registers are volatile, i.e., they lose their state when the device is powered down. All PIO-related registers can be read like any data memory.
PAGE 10
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO PIO Activity Latch State Register ADDR b7 b6 b5 b4 b3 b2 b1 b0 0222h 0 0 0 0 0 0 AL1 AL0 The data in this register represents the current state of the PIO activity latches. This register is read using the Read Memory command. This register is read-only. Each bit is associated with the activity latch of the respective PIO channel. Bits 2 to 7 have no function; they always read 0.
PAGE 11
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Conditional Search Channel Polarity Selection Register ADDR b7 b6 b5 b4 b3 b2 b1 b0 0224h 0 0 0 0 0 0 SP1 SP0 The data in this register specifies the polarity of each selected PIO channel for the device to respond to the conditional search command. This register can only be written through the Write Registers command.
PAGE 12
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO ADDRESS REGISTERS AND TRANSFER STATUS The DS28E04-100 employs three address registers, called TA1, TA2, and E/S (Figure 8). Registers TA1 and TA2 must be loaded with the target address to which the data will be written or from which data is read. Register E/S is a read-only transfer-status register, used to verify data integrity of write commands. The lower five bits of the E/S register indicate the Ending Offset within the 32-byte scratchpad.
PAGE 13
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO MEMORY/CONTROL FUNCTION COMMANDS The Memory/Control Function Flow Chart (Figure 9) describes the protocols necessary to access the memory and the PIO pins of the DS28E04-100. Examples on how to use these functions are included at the end of this document. The communication between master and DS28E04-100 takes place either at standard speed (default, OD = 0) or at Overdrive peed (OD = 1).
PAGE 14
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 9-1. Memory/Control Function Flow Chart From ROM Functions Flow Chart (Figure 14) Bus Master TX Memory Function Command 0Fh Write Scratchpad ? To Figure 9 nd 2 Part N Applies only if the page is not write protected or in EPROM mode. If writeprotected, then the DS28E04 copies the data byte from the target address into the scratchpad.
PAGE 15
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 9-2. Memory/Control Function Flow Chart (continued) From Figure 9 st 1 Part AAh Read ScratchPad ? N To Figure 9 rd 3 Part Y Bus Master RX TA1 (T7:T0), TA2 (T15:T8) and E/S Byte DS28E04 sets Scratchpad Offset = (T4:T0) Bus Master RX Data Byte from Scratchpad Offset DS28E04 Increments Scratchpad Offset Master TX Reset ? See note in Write Scratchpad flow chart for additional details. Y N N Scrpad.
PAGE 16
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 9-3. Memory/Control Function Flow Chart (continued) From Figure 9 nd 2 Part 55h Copy ScratchPad ? To Figure 9 th 4 Part N Y Bus Master TX TA1 (T7:T0), TA2 (T15:T8) and E/S Byte Y Auth. Code Match ? Applicable to all R/W memory locations.
PAGE 17
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 9-4.
PAGE 18
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 9-5.
PAGE 19
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 9-6.
PAGE 20
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO READ MEMORY [F0h] The Read Memory command is the general function to read data from the DS28E04-100. After issuing the command, the master must provide a 2-byte target address in the range of 0000h to 0225h. After these two bytes, the master reads data beginning from the target address and may continue until address 0225h. If the master continues reading, the result will be logic 1s.
PAGE 21
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO PIO ACCESS WRITE [5Ah] The PIO Access Write command is the only way to write to the PIO output-latch state register (address 0221h), which controls the open-drain output transistors of the PIO channels. In an endless loop, this command first writes new data to the PIO and then reads back the PIO status. The implicit read-after-write can be used by the master for status verification.
PAGE 22
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 12. PIO Access Pulse Timing Diagram MS 2 bits of inverted Selection Mask VTH IO tREH+x PIO LS 2 bits of confirmation byte (AAh) POL=1 tPULSE POL=0 RESET ACTIVITY LATCHES [C3h] Each PIO channel includes an activity latch that is set whenever there is a state transition at a PIO pin of duration greater than tPWMIN. This change can be caused by an external event/signal or by writing to the PIO or by generating a pulse.
PAGE 23
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 13. Hardware Configuration BUS MASTER VPUP DS28E04 1-Wire PORT RPUP RX DATA TX RX = RECEIVE Open-Drain Port Pin RX TX 11µA Max.
PAGE 24
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO SEARCH ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their device ID numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the device ID numbers of all slave devices. For each bit of the device ID number, starting with the least significant bit, the bus master issues a triplet of time slots.
PAGE 25
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 14-1. ROM Functions Flow Chart Bus Master TX Reset Pulse From Memory Functions Flow Chart (Figure 9) From Figure 14, 2 OD Reset Pulse? N nd Part OD = 0 Y Bus Master TX ROM Function Command 33h Read ROM Command? Y RC = 0 DS28E04 TX Presence Pulse N 55h Match ROM Command? F0h Search ROM Command? N Y To Figure 14 nd 2 Part ECh Cond.
PAGE 26
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 14-2.
PAGE 27
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO OVERDRIVE MATCH ROM [69h] The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at Overdrive speed allows the bus master to address a specific DS28E04-100 on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS28E04-100 that exactly matches the 64-bit ROM sequence responds to the subsequent Memory/Control Function command.
PAGE 28
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Read/Write Time Slots Data communication with the DS28E04-100 takes place in time slots, which carry a single bit each. Write time slots transport data from bus master to slave. Read time slots transfer data from slave to master. Figure 16 illustrates the definitions of the write and read time slots. All communication begins with the master pulling the data line low.
PAGE 29
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Master-to-Slave For a write-one time slot, the voltage on the data line must have crossed the VTH threshold before the write-one low time tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the VTH threshold until the write-zero low time tW0LMIN is expired. For the most reliable communication, the voltage on the data line should not exceed VILMAX during the entire tW0L or tW1L window.
PAGE 30
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 17. Noise Suppression Scheme tREH VPUP tREH VTH VHY Case A 0V Case B tGL Case C tGL CRC GENERATION With the DS28E04-100 there are two different types of CRCs. One CRC is an 8-bit type and is stored in the most significant byte of the 64-bit ROM.
PAGE 31
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO Figure 18.
PAGE 32
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL—COLOR CODES Master to slave Slave to master Programming WRITE SCRATCHPAD (CANNOT FAIL) RST PD Select WS TA <32 – T4:T0 bytes> CRC16\ FF loop READ SCRATCHPAD (CANNOT FAIL) RST PD Select RS TA-E/S CRC16\ FF loop COPY SCRATCHPAD 1-Wire POWERED (SUCCESS) RST PD Select CPS TA-E/S wait tPROGMAX AA loop COPY SCRATCHPAD (INVALID ADDRESS OR PF = 1 OR COPY PROTECT
PAGE 33
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO PIO ACCESS READ (CANNOT FAIL) RST PD Select PIOR <32 bytes PIO data> CRC16\ Loop until master sends Reset Pulse PIO ACCESS WRITE (SUCCESS) RST PD Select PIOW Loop until master sends Reset Pulse PIO ACCESS WRITE (INVALID DATA BYTE) RST PD Select PIOW FF loop PIO ACCESS PULSE (SUCCESS) RST PD Select PIOP
PAGE 34
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO MEMORY FUNCTION EXAMPLE Write 5 bytes to memory page 1, starting at address 0021h. Read the entire memory and the PIO-related registers.
PAGE 35
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO PIO ACCESS READ EXAMPLE Read the state of the PIOs 32 times.
PAGE 36
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO PIO ACCESS PULSE EXAMPLE Generate a pulse on PIO1. Both PIOs are pulled high to VCC by a resistor. POL = 1. VCC power is present.
PAGE 37
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO REVISION HISTORY REVISION DATE 102704 12/11 DESCRIPTION Initial release Changed the Ordering Information for lead(Pb)-free product; updated the lead temperature and soldering temperature; extended the storage temperature range. In the Electrical Characteristics table applied Note 19 to the tW0L specification, deleted ε from the tW1L specification, increased the data retention time, added more details to notes 10, 19 and 20, and added notes 23, 24.