Datasheet

DS28CM00: I²C/SMBus Silicon Serial Number
4 of 9
Figure 1. Block Diagram
SCL
SDA
ROM
Registration
Number
Control
Register
Serial
Interface
V
CC
GND
Figure 2. Memory Map
ADDRESS TYPE ACCESS DESCRIPTION
00h ROM Read Device Family Code (70h)
01h ROM Read Serial Number, bits 0 to 7
02h ROM Read Serial Number, bits 8 to 15
03h ROM Read Serial Number, bits 16 to 23
04h ROM Read Serial Number, bits 24 to 31
05h ROM Read Serial Number, bits 32 to 39
06h ROM Read Serial Number, bits 40 to 47
07h ROM Read CRC of Family Code and 48-bit Serial Number
08h SRAM R/W Control Register
Unique Registration Number
Each DS28CM00 has a unique Registration Number that is 64 bits long. The registration number begins with the
family code at address 00h followed by the 48-bit serial number (LS-byte at the lower address) and ends at
address 07h with the CRC (Cyclic Redundancy Check) of the first 56 bits. This CRC is generated using the
polynomial X
8
+ X
5
+ X
4
+ 1. Additional information about CRCs is available in Application Note 27. The ROM
Registration Number is not related to the I²C slave address of the device.
Control Register
The Control Register at address 08h allows switching between I²C mode and SMBus mode. Only the LS bit of this
register, referred to as the CM bit, has a function. The other 7 bits always read 0 and cannot be changed. When the
CM bit is set to 1 (power-on default), the device is in SMBus mode, which enables the bus timeout function. Setting
the CM bit to 0 puts the device in I²C mode, where the timeout function is disabled. In SMBus mode, the serial
interface times out and is internally reset if SCL is stuck (high or low) or if SDA is stuck low for the duration of
t
TIMEOUT
or longer. This reset turns the SDA line into an input, ensuring that the device is ready to recognize a
communication start condition.
ADDR b7 b6 b5 b4 b3 b2 b1 b0
08h
0 0 0 0 0 0 0 CM