Datasheet

DS2782
20 of 28
CONTROL REGISTER
All CONTROL register bits are read and write accessible. The CONTROL register is recalled from Parameter
EEPROM memory at power-up. Register bit values can be modified in shadow RAM after power-up. Shadow RAM
values can be saved as the power up default values by using the Copy Data command.
Figure 19. Control Register Format
ADDRESS 60h BIT DEFINITION
FIELD BIT FORMAT ALLOWABLE VALUEs
Reserved
7 Undefined
UVEN
6 Read/Write
Under Voltage SLEEP Enable
0: Disables transition to SLEEP mode based on VIN voltage
1: Enables transition to SLEEP mode if,
VIN < V
SLEEP
AND SDA, SCL stable at either logic level for t
SLEEP
PMOD
5 Read/Write
Power Mode Enable
0: Disables transition to SLEEP mode based on SDA, SCL logic state
1: Enables transition to SLEEP mode if SDA, SCL at a logic low for
t
SLEEP
Reserved
0:4 Undefined
SPECIAL FEATURE REGISTER
All Special Feature Register bits are read and write accessible, with default values specified in each bit definition.
Figure 20. Special Feature Register Format
ADDRESS 15h BIT DEFINITION
FIELD BIT FORMAT ALLOWABLE VALUES
Reserved
2:7 Undefined
SAWE
1 Read/Write
Slave Address Write Enable
0: Disables writes to the Slave Address Register
1: Enables writes to the Slave Address Register
Power-up default: 0 (writes disabled)
PIOSC
0 Read/Write
PIO Sense and Control
Read values
0: PIO pin ≤ Vil
1: PIO pin ≥ Vih
Write values
0: Activates PIO pin open-drain output driver, forcing the PIO pin low
1: Disables the output driver, allowing the PIO pin to be pulled high or
used as an input
Power-up and SLEEP mode default: 1 (PIO pin is hi-Z)
Note: PIO pin has weak pulldown