Datasheet

DS2782
19 of 28
STATUS REGISTER
The STATUS register contains bits which report the device status. The bits can be set internally by the DS2782.
The CHGTF, AEF, SEF, LEARNF and VER bits are read only bits which can be cleared by hardware. The UVF and
PORF bits can only be cleared via the 2-Wire interface.
Figure 18. Status Register Format
ADDRESS 01h BIT DEFINITION
FIELD BIT FORMAT ALLOWABLE VALUES
CHGTF
7 Read Only
Charge Termination Flag
Set to 1 when: ( VOLT > VCHG ) AND ( 0 < IAVG < IMIN ) continuously
for a period between two IAVG register updates ( 28s to 56s ).
Cleared to 0 when: RARC < 90%
AEF
6 Read Only
Active Empty Flag
Set to 1 when: VOLT < VAE
Cleared to 0 when: RARC > 5%
SEF
5 Read Only
Standby Empty Flag
Set to 1 when: RSRC < 10%
Cleared to 0 when: RSRC > 15%
LEARNF
4 Read Only
Learn Flag – When set to 1, a charge cycle can be used to learn battery
capacity.
Set to 1 when: ( VOLT falls from above VAE to below VAE ) AND
( CURRENT > IAE )
Cleared to 0 when: ( CHGTF = 1 ) OR ( CURRENT < +100µV ) OR
( ACR = 0 **) OR ( ACR written or recalled from EEPROM) OR ( SLEEP
Entered )
Reserved
3 Read Only Undefined
UVF
2 Read / Write *
Under-Voltage Flag
Set to 1 when: VOLT < V
SLEEP
Cleared to 0 by: User
PORF
1 Read / Write *
Power-On Reset Flag – Useful for reset detection, see text below.
Set to 1 upon Power-Up by hardware.
Cleared to 0 by: User
Reserved
0 Read Only Undefined
* - This bit can be set by the DS2782, and may only be cleared via the 2-Wire interface.
** - LEARNF is only cleared if ACR reaches 0 after VOLT < VAE.