Datasheet

DS2746 Low-Cost 2-Wire Battery Monitor
7 of 17
Figure 4. APPLICATION EXAMPLE
2.5V
R
SNS
(1)
10nF
DS2746
AIN0
VINVOUT
AIN1
SDA
VSS
SCL
Pack+
Pack-
System
Serial
Bus
(1) Optional for 8kV/15kV ESD
Protection IC
(Li+/Polymer)
1nF 1nF
Therm
PackID
System
VDD
System
VSS
SNS
VDD
(1)
5.6V
1K
CTG
1K
1K
150
POWER MODES
The DS2746 operates in one of two power modes: active and sleep. While in active mode, the DS2746 operates as
a high-precision battery monitor with voltage, auxiliary inputs, current and accumulated current measurements
acquired continuously and the resulting values updated in the measurement registers. Read and write access is
allowed to all registers. In sleep mode, the DS2746 operates in a low-power mode with no measurement activity.
The DS2746 operating mode transitions from SLEEP to ACTIVE when:
( SCL > V
IH
) OR ( SDA > V
IH
)
The DS2746 operating mode transitions from ACTIVE to SLEEP when:
SMOD = 1 AND [ ( SCL < V
IL
) AND ( SDA < V
IL
) ] for t
SLEEP
CAUTION: If SMOD = 1, a pull-up resistor is required on SCL and SDA in order to ensure that the DS2746
transitions from SLEEP to ACTIVE mode when the battery is charged. If the bus is not pulled up, the DS2746
remains in SLEEP and cannot accumulate the charge current.
MEASUREMENT SEQUENCE
The DS2746 uses seperate A/D converters to make voltage and current measurements. Each A/D converter
operates completely independent of the other, allowing measurements of voltage and current to be made in
parallel. Current Measurements are made at a resolution of 13 bits plus sign bit. The current register is updated
every 878ms with the average for that time period.
All Voltage Measurements are made at a resolution of 11 bits plus sign bit. The DS2746 continouly cycles through
measuring V
IN
, AIN0, and AIN1 in that order. Voltage measurement of each input requires 220ms to complete. A
full sequence of voltage measurements requires 660ms to complete. V
OUT
is active for a precharge time of t
PRE
before the AIN0 measurement time occurs. The V
OUT
pin is enabled during the entire AIN0 and AIN1 measurement
sequence as long as the V
ODIS
(V
OUT
Disable) bit is cleared. See Figure 5.