Datasheet

DS2746 Low-Cost 2-Wire Battery Monitor
3 of 17
SCL, SDA V
PIN
= 0.4V
Input Capacitance:
SCL, SDA
C
BUS
50 pF
Bus Low Timeout t
SLEEP
(Note 3) 1.5 2.2 S
DC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE
(V
DD
= 2.5V to 4.5V, T
A
= -20°C to +70°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency
f
SCL
(Note 4) 0 400 KHz
Bus Free Time Between a
STOP and START Condition
t
BUF
1.3 µs
Hold Time (Repeated)
START Condition
t
HD:STA
(Note 5) 0.6 µs
Low Period of SCL Clock
t
LOW
1.3 µs
High Period of SCL Clock
t
HIGH
0.6 µs
Setup Time for a Repeated
START Condition
t
SU:STA
0.6 µs
Data Hold Time
t
HD:DAT
(Note 6, 7) 0 0.9 µs
Data Setup Time
t
SU:DAT
(Note 6) 100 ns
Rise Time of Both SDA and
SCL Signals
t
R
20 + 0.1C
B
300 ns
Fall Time of Both SDA and
SCL Signals
t
F
20 + 0.1C
B
300 ns
Setup Time for STOP
Condition
t
SU:STO
0.6 µs
Spike Pulse Widths
Suppressed by Input Filter
t
SP
(Note 8) 0 50 ns
Capacitive Load for Each Bus
Line
C
B
(Note 9) 400 pF
SCL, SDA Input Capacitance C
BIN
60 pF
Note 1: All voltages are referenced to V
SS
.
Note 2: Offset specified after auto-calibration cycle and Current Offset Bias register = 0x00.
Note 3: The DS2746 enters the sleep mode 1.5s to 2.2s after ( SCL < V
il
.) AND ( SDA < V
il
).
Note 4: Timing must be fast enough to prevent the DS2746 from entering sleep mode due t
o bus low for period > t
SLEEP
.
Note 5: f
SCL
must meet the minimum clock low time plus the rise/fall times.
Note 6: The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
Note 7: This device internally provides a hold time of at least 100ns for the SDA signal (referr
ed to the VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 8: Filters on SDA and SCL suppress noise spikes at t
he input buffers and dela
y the sampling instant.
Note 9: C
b
– total capacitance of one bus line in pF.
Note 10:
The AIN
GERR
spec is only valid when this equation is satisfied: (V
AINx
+ 2V
OUT
)  (11.6V - (T
A
- 25C)10mV/C). See Figure 1.
Note 11: Accuracy specification valid for V
SS
- SNS ≥ ±2.5mV, below which offset error is dominant.