Datasheet

DS26521 Single T1/E1/J1 Transceiver
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FRAMER REGISTER LIST
ADDRESS NAME DESCRIPTION R/W
085h RESCR Receive Elastic Store Control Register R/W
086h ERCNT Error-Counter Configuration Register R/W
087h RHFC Receive HDLC FIFO Control Register R/W
088h RIBOC Receive Interleave Bus Operation Control Register R/W
089h T1RSCC In-Band Receive Spare Control Register (T1 Mode Only) R/W
08Ah RXPC Receive Expansion Port Control Register R/W
08B RBPBS Receive BERT Port Bit Suppress Register R/W
08Ch–08Fh — Reserved —
090h RLS1 Receive Latched Status Register 1 R/W
091h RLS2 Receive Latched Status Register 2 R/W
092h RLS3 Receive Latched Status Register 3 R/W
093 RLS4 Receive Latched Status Register 4 R/W
094h RLS5 Receive Latched Status Register 5 (HDLC) R/W
095h — Reserved —
RLS7 Receive Latched Status Register 7 (T1 Mode)
096h
RLS7 Receive Latched Status Register 7 (E1 Mode)
R/W
097h — Reserved —
098h RSS1 Receive-Signaling Status Register 1 R/W
099h RSS2 Receive-Signaling Status Register 2 R/W
09Ah RSS3 Receive-Signaling Status Register 3 R/W
09Bh RSS4 Receive-Signaling Status Register 4 (E1 Mode Only) R/W
09Ch T1RSCD1 Receive Spare Code Definition Register 1 (T1 Mode Only) R/W
09Dh T1RSCD2 Receive Spare Code Definition Register 2 (T1 Mode Only) R/W
09Eh — Reserved —
09Fh RIIR Receive Interrupt Information Register R/W
0A0h RIM1 Receive Interrupt Mask Register 1 R/W
0A1h RIM2 Receive Interrupt Mask Register 2 (E1 Mode Only) R/W
RIM3 Receive Interrupt Mask Register 3 (T1 Mode)
0A2h
RIM3 Receive Interrupt Mask Register 3 (E1 Mode)
R/W
0A3h RIM4 Receive Interrupt Mask Register 4 R/W
0A4h RIM5 Receive Interrupt Mask Register 5 (HDLC) R/W
0A5h — Reserved —
0A6h RIM7 Receive Interrupt Mask Register 7 (T1 Mode) R/W
0A7h — Reserved —
0A8h RSCSE1 Receive-Signaling Change of State Enable Register 1 R/W
0A9h RSCSE2 Receive-Signaling Change of State Enable Register 2 R/W
0AAh RSCSE3 Receive-Signaling Change of State Enable Register 3 R/W
0ABh RSCSE4 Receive-Signaling Change of State Enable Register 4 (E1 Mode Only) —
0ACh T1RUPCD1 Receive Up Code Definition Register 1 (T1 Mode Only) R/W
0ADh T1RUPCD2 Receive Up Code Definition Register 2 (T1 Mode Only) R/W
0AEh T1RDNCD1 Receive Down Code Definition Register 1 (T1 Mode Only) R/W
0AFh T1RDNCD2 Receive Down Code Definition Register 2 (T1 Mode Only) R/W
0B0h RRTS1 Receive Real-Time Status Register 1 R
0B1h — Reserved —
RRTS3 Receive Real-Time Status Register 3 (T1 Mode)
0B2h
RRTS3 Receive Real-Time Status Register 3 (E1 Mode)
R
0B3h — Reserved —
0B4h RRTS5 Receive Real-Time Status Register 5 (HDLC) R
0B5h RHPBA Receive HDLC Packet Bytes Available Register R
0B6h RHF Receive HDLC FIFO Register R
0B7h–0BFh — Reserved —
0C0h RBCS1 Receive Blank Channel Select Register 1 R/W