Datasheet

DS26521 Single T1/E1/J1 Transceiver
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9. DEVICE REGISTERS
Thirteen address bits are used to control the settings of the registers. The address map is compatible with the
Dallas Semiconductor dual framer product, DS26522.
The registers control functions of the framers, LIU, and BERT within the DS26521. Global registers (applicable to
the transceiver and BERT) are located within the address space of the framer.
The register details are provided in the following tables. Thirteen address bits are needed to decode the register
range. However, address bits A9, A10, and A11 are internally pulled to ground and do not come out to a pin. These
bits are not needed to access any available register on the DS26521. The address range was mapped this way to
preserve software compatibility with the register maps of the TEX-series transceiver family of devices (DS26528,
DS26524, and DS26522). This allows for reuse of software developed for the DS26528 octal, for example, without
remapping the registers.
All interrupt information register bits are real-time bits that clear once the appropriate interrupt has been serviced
and cleared, as long as no additional, unmasked interrupt condition is present in the associated status register.
All latched status bits must be cleared by the host writing a 1 to the bit location of the interrupt condition that has
been serviced. Latched status bits that have been masked via interrupt mask registers are masked from the
interrupt information registers.
9.1 Register Listings
Table 9-1. Register Address Ranges
ADDRESS RANGE (IN BINARY)*
BLOCK
ADDRESS
RANGE
(IN HEX)
A12 A8 A[7:4] A[3:0] A12 A8 A[7:4] A[3:0]
Receive
Framer
0000–00EF 0 0 0000 0000 0 0 1110 1111
Global
Registers
00F0–00FF 0 0 1111 0000 0 0 1111 1111
Transmit
Framer
0100–01EF 0 1 0000 0000 0 1 1110 1111
LIU 1000–1017 1 0 0000 0000 1 0 0000 0111
TEST 1018–101F 1 0 0000 1000 1 0 0001 1111
BERT 1100–110F 1 1 0000 0000 1 1 0000 1111
*A9, A10, and A11 are internally pulled low to provide software compatibility with other TEX-series transceivers.