Datasheet
DS26521 Single T1/E1/J1 Transceiver
35 of 258
8.8.1.7 Mapping E1 Channels onto a 1.544MHz Backplane
The user can use the RSCLKM bit (
RIOCR.4) to enable the receive elastic store to operate with a 1.544MHz
backplane (24 channels / frame + F-bit). In this mode the user can choose which of the E1 time slots will be
ignored (not transmitted onto RSER) by programming the Receive Blank Channel Select registers
(
RBCS1:RBCS4). A logic 1 in the associated bit location causes the elastic store to ignore the incoming E1 data for
that channel. Typically the user will want to program eight channels to be ignored. The default (power-up)
configuration will ignore channels 25 to 32, so that the first 24 E1 channels are mapped into the 24 channels of the
1.544MHz backplane. In this mode the F-bit location at RSER is always set to 1.
For example, if the user wants to ignore E1 time slots 0 (channel 1) and TS16 (channel 17), the
RBCS1:RBCS4
registers would be programmed as follows:
RBCS1 = 01h
RBCS2 = 00h
RBCS3 = 01h
RBCS4 = FCh
8.8.2 IBO Multiplexer
The DS26521 supports IBO operation by tri-stating the RSER and RSIG pins at the appropriate times for external
bus wiring. This mode of operation is enabled in the
RIBOC and TIBOC registers.
Note that the channel block signals TCHBLK and RCHBLK are output at the rate of the IBO selection.
Table 8-4. Registers Related to the IBO Multiplexer
REGISTER
FRAMER
ADDRESSES
FUNCTION
Global Transceiver Control Register 1
(
GTCR1)
0F0h The GIBOE bit enables IBO.
Receive Interleave Bus Operation
Control Register (
RIBOC)
088h
This register can be used for control of how many
framers and the corresponding speed for the IBO
links for the receiver.
Transmit Interleave Bus Operation
Control Register (
TIBOC)
188h
This register can be used for control of how many
framers and the corresponding speed for the IBO
links for the transmitter.
Figure 8-11. IBO Example Circuit
RSER
RSIG
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
DS26521
Backplane
Interface
RSER
RSIG
RSYNC
RSYSCLK
TSER
TSIG
TSSYNC
TSYSCLK
RSER1
RSIG1
RSYNC1
RSYSCLK
TSER1
TSIG1
TSSYNCIO
TSYSCLK
DS26521
Backplane
Interface
Note: This figure shows a typical application where two DS26521s are on a single 4.096MHz backplane.