Datasheet

DS26521 Single T1/E1/J1 Transceiver
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8.2 Clock Structure
The user should provide a system clock to the MCLK input of 2.048MHz, 1.544MHz, or a multiple of up to 8x the T1
and E1 frequencies. To meet many specifications, the MCLK source should have ±50ppm accuracy.
8.2.1 Backplane Clock Generation
The DS26521 provides facility for provision of BPCLK at 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz (see Figure
8-9
). The Global Transceiver Clock Control register (GTCCR) is used to control the backplane clock generation.
This register is also used to program REFCLKIO as an input or output. REFCLKIO can output MCLKT1 or
MCLKE1 as shown in
Figure 8-9.
This backplane clock and frame pulse (TSSYNCIO) can be used by the DS26521 and other IBO-equipped devices
as an IBO bus master. Hence, the DS26521 provides the 8kHz sync pulse and 4MHz, 8MHz, and 16MHz clock.
This can be used by the link layer devices and frames connected to the IBO bus.
Figure 8-9. Backplane Clock Generation
MULTIPLEXER
CLOCK
RCLK
PRESCALER
PLL
MCLKT1
MCLKE1
MCLK
BPREFSEL[3:0]
CLK
GEN
REFCLKIO
REFCLKIO
BPCLK
BPCLK[1:0]
BFREQSEL
TSSYNCIO
The reference clock for the backplane clock generator can be as follows:
• External Master Clock. A prescaler can be used to generate T1 or E1 frequency.
• External Reference Clock REFCLKIO. This allows for multiple DS26521s to use the backplane clock from
a common reference.
• Internal LIU recovered RCLK.
• The clock generator can be used to generate BPCLK of 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz
for the IBO.
• If MCLK or RCLK are used as a reference, REFCLKIO can be used to provide a 2.048MHz or 1.544MHz
clock for external use.