Datasheet

DS26521 Single T1/E1/J1 Transceiver
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12.2 JTAG Interface Timing
Table 12-5. JTAG Interface Timing
(V
DD
= 3.3V ±5%, T
A
= -40°C to +85°C.) (Note 1) (See Figure 12-12.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
JTCLK Clock Period
t1 1000 ns
JTCLK Clock High:Low Time
t2:t3 (Note 2) 50 500 ns
JTCLK to JTDI, JTMS Setup Time
t4 5 ns
JTCLK to JTDI, JTMS Hold Time
t5 2 ns
JTCLK to JTDO Delay
t6 2 50 ns
JTCLK to JTDO High-Impendance Delay
t7 2 50 ns
JTRST Width Low Time
t8 100 ns
Note 1: The timing parameters in this table are guaranteed by design (GBD).
Note 2: Clock can be stopped high or low.
Figure 12-12. JTAG Interface Timing Diagram
JTCL
K
t1
JTD0
t4 t5
t2 t3
t7
JTDI, JTMS,
J
TRS
T
t6
JTRST
t8