Datasheet

DS26521 Single T1/E1/J1 Transceiver
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Figure 12-5. SPI Interface Timing Diagram
NOTE 1: CLOCK EDGE REFERENCE TO DATA CONTROLLED BY CPHA AND CPOL SETTINGS. SEE THE FUNCTIONAL
TIMING DIAGRAMS.
NOTE 2: NOT DEFINED, BUT USUALLY MSB OF CHARACTER JUST RECEIVED.
CS
INPUT
SPI_SCLK
SPI_SCLK
1
MOSI
INPUT
MISO
OUTPUT
MSB
BITS
13:0
SLAVE
MSB
BITS 6:1
NOTE 2
BIT 14
t1
t4
t5
t2
t3
SLAVE
LSB
t8
t6
t7
t9
t10