Datasheet

DS26521 Single T1/E1/J1 Transceiver
240 of 258
12.1.2 SPI Bus Mode
Table 12-2. SPI Bus Mode Timing
(See Note 1, Figure 12-5.)
SYMBOL
(2)
CHARACTERISTIC
(3)
SYMBOL MIN MAX UNITS
Operating Frequency
Slave
f
BUS(S)
— 4 MHz
t1 Cycle Time: Slave t
CYC(S)
250 — ns
t2 Enable Lead Time t
LEAD(S)
15 — ns
t3 Enable Lag Time t
LAG(S)
15 — ns
t4
Clock (CLK) High Time
Slave
t
CLKH(S)
t5
Clock (CLK) Low Time
Slave
t
CLKL(S)
t6
Data Setup Time (Inputs)
Slave
t
SU(S)
5 — ns
t7
Data Hold Time (Inputs)
Slave
t
H(S)
15 — ns
t8 Disable Time, Slave
(4)
t
DIS(S)
— 25 ns
t9
Data Valid Time, After Enable Edge
Slave
(5)
t
V(S)
— 40 ns
t10
Data Hold Time, Outputs, After Enable Edge
Slave
t
HD(S)
5 — ns
Note 1: The timing parameters in this table are guaranteed by design (GBD).
Note 2: Symbols refer to dimensions in
Figure 12-5.
Note 3: 100pF load on all SPI pins.
Note 4: Hold time to high-impedance state.
Note 5: With 100pF on all SPI pins.