Datasheet

DS26521 Single T1/E1/J1 Transceiver
24 of 258
NAME PIN TYPE FUNCTION
TEST
JTRST
47 I, Pullup
JTAG Reset. JTRST is used to asynchronously reset the test access port
controller. After power-up,
JTRST must be toggled from low to high. This action
sets the device into the JTAG DEVICE ID mode. Pulling
JTRST low restores
normal device operation.
JTRST is pulled high internally via a 10kΩ resistor
operation. If boundary scan is not used, this pin should be held low.
JTMS 46 I, Pullup
JTAG Mode Select. This pin is sampled on the rising edge of JTCLK and is used
to place the test access port into the various defined IEEE 1149.1 states. This pin
has a 10k
Ω pullup resistor.
JTCLK 45 I
JTAG Clock. This signal is used to shift data into JTDI on the rising edge and out
of JTDO on the falling edge.
JTDI 44 I, Pullup
JTAG Data In. Test instructions and data are clocked into this pin on the rising
edge of JTCLK. This pin has a 10k
Ω pullup resistor.
JTDO 43
O, High
impedance
JTAG Data Out. Test instructions and data are clocked out of this pin on the falling
edge of JTCLK. If not used, this pin should be left unconnected.
SCANMODE 3 I
Scan Mode. This pin should be connected to ground for normal operation.
SCAN_EN 4 I
Scan Enable. This pin should be connected to ground for normal operation.
POWER SUPPLIES
ATVDD 5 —
3.3V Analog Transmit Power Supply. This V
DD
input is used for the transmit LIU
section of the DS26521.
ATVSS 8 —
Analog Transmit V
SS
. This pin is used for transmit analog V
SS
.
ARVDD 9 —
3.3V Analog Receive Power Supply. This V
DD
input is used for the receive LIU
section of the DS26521.
ARVSS 12 —
Analog Receive V
SS
. This pin is used for analog V
SS
for the receiver.
ACVDD 40 —
Analog Clock Conversion V
DD
. This V
DD
input is used for the clock conversion
unit of the DS26521.
ACVSS 41 —
Analog Clock V
SS
. This pin is used for clock converter analog V
SS
.
DVDD 21 —
3.3V Power Supply for the Digital Framer
DVSS 22 —
Digital Ground for the Framer