Datasheet

DS26521 Single T1/E1/J1 Transceiver
237 of 258
12. AC TIMING CHARACTERISTICS
Unless otherwise noted, all timing numbers assume 20pF test load on output signals, 40pF test load on bus
signals.
12.1 Microprocessor Bus AC Characteristics
12.1.1 Parallel Port Mode
Table 12-1. AC Characteristics—Microprocessor Bus Timing
(V
DD
= 3.3V ±5%, T
A
= -40°C to +85°C.) (Note 1) (See Figure 12-1, Figure 12-2, Figure 12-3, and
Figure 12-4.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Setup Time for A12, A[8:0] Valid to CSBn
Active
t1 0 ns
Setup Time for CSB Active to Either RDB,
or
WRB Active
t2 0 ns
Delay Time from Either RDB or DSB
Active to D[7:0] Valid
t3 (Note 2) 125 ns
Hold Time from Either RDB or WRB
Inactive to
CSB Inactive
t4 0 ns
Hold Time from CSB or RDB or DSB
Inactive to D[7:0] Tri-State
t5 5 20 ns
Wait Time from WRB Active to Latch Data
t6
40 ns
Data Setup Time to WRB Inactive
t7 10 ns
Data Hold Time from WRB Inactive
t8 5 ns
Address Hold from WRB Inactive
t9 0 ns
Write Access to Subsequent Write/Read
Access Delay Time
t10 (Note 2) 80 ns
Note 1: The timing parameters in this table are guaranteed by design (GBD).
Note 2: If supplying a 1.544MHz MCLK, the FREQSEL bit must be set to meet this timing.