Datasheet

DS26521 Single T1/E1/J1 Transceiver
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Figure 10-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode
NOTE 1: 4.096MHz BUS CONFIGURATION.
NOTE 2: 8.192MHz BUS CONFIGURATION.
NOTE 3: RSYNC IS IN THE INPUT MODE (RIOCR.2 = 0).
NOTE 4: SHOWS SYSTEM IMPLEMENTATION WITH MULTIPLE DS26521 CORES DRIVING BACKPLANE.
NOTE 5: THOUGH NOT SHOWN, TCHCLK CONTINUES TO MARK THE CHANNEL LSB FOR THE FRAMER'S ACTIVE PERIOD.
NOTE 6: THOUGH NOT SHOWN, TCHBLK CONTINUES TO MARK THE BLOCKED CHANNELS FOR THE FRAMER’S ACTIVE PERIOD.
RSER
LSB
SYSCLK
RSYNC
FRAMER 3, CHANNEL 32
MSB
LSB
FRAMER 0, CHANNEL 1
RSI G
FRAMER 3, CHANNEL 32 FRAMER 0, CHANNEL 1
MSB
LSB
FRAMER 1, CHANNEL 1
FRAMER 1, CHANNEL 1
3
RSER
RSYNC
RSI G
RSER
RSI G
FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2
1
1
2
2
BIT DETAIL
FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2
FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2
FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2
ABCD ABCD ABCD