Datasheet

DS26521 Single T1/E1/J1 Transceiver

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LLSR

LIU Latched Status Register

1005h

Bit # 7 6 5 4 3 2 1 0

Name JALTC OCC SCC LOSC JALTS OCD SCD LOSD

Default 0 0 0 0 0 0 0 0

Note: All bits in this register are latched and can create interrupts.

Bit 7: Jitter Attenuator Limit Trip Clear (JALTC). This latched bit is set when a jitter attenuator limit trip condition

was detected and then removed.

Bit 6: Open-Circuit Clear (OCC).

This latched bit is set when an open-circuit condition was detected at TTIP and

TRING and then removed.

Bit 5: Short-Circuit Clear (SCC). This latched bit is set when a short-circuit condition was detected at TTIP and

TRING and then removed.

Bit 4: Loss of Signal Clear (LOSC). This latched bit is set when a loss-of-signal condition was detected at RTIP

and RRING and then removed.

Bit 3: Jitter Attenuator Limit Trip Set (JALTS). This latched bit is set when the jitter attenuator limit trip condition

is detected.

Bit 2: Open-Circuit Detect (OCD).

This latched bit is set when an open-circuit condition is detected at TTIP and

TRING. This bit is not functional in T1 CSU operating modes (T1 LBO 5, LBO 6, and LBO 7).

Bit 1: Short-Circuit Detect (SCD). This latched bit is set when a short-circuit condition is detected at TTIP and

TRING. This bit is not functional in T1 CSU operating modes (T1 LBO 5, LBO 6, and LBO 7).

Bit 0: Loss of Signal Detect (LOSD).

This latched bit is set when an LOS condition is detected at RTIP and

RRING.