Datasheet

DS26521 Single T1/E1/J1 Transceiver
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9.5 LIU Register Definitions
Table 9-14. LIU Register Set
ADDRESS NAME DESCRIPTION R/W
1000h LTRCR LIU Transmit Receive Control Register R/W
1001h LTITSR LIU Transmit Impedance and Pulse Shape Selection Register R/W
1002h LMCR LIU Maintenance Control Register R/W
1003h LRSR LIU Real Status Register R
1004h LSIMR LIU Status Interrupt Mask Register R/W
1005h LLSR LIU Latched Status Register R/W
1006h LRSL LIU Receive Signal Level Register R
1007h LRISMR LIU Receive Impedance and Sensitivity Monitor Register R/W
1008h–101Fh — Reserved —
Note: Reserved registers should only be written with all zeros.
Register Name:
LTRCR
Register Description:
LIU Transmit Receive Control Register
Register Address:
1000h
Bit # 7 6 5 4 3 2 1 0
Name — — — JADS JAPS1 JAPS0 T1J1E1S LSC
Default 0 0 0 0 0 0 0 0
Bit 4: Jitter Attenuator Depth Select (JADS).
0 = Jitter attenuator FIFO depth set to 128 bits.
1 = Jitter attenuator FIFO depth set to 32 bits. Use for delay-sensitive applications.
Bits 3 and 2: Jitter Attenuator Position Select 1 and 0 (JAPS[1:0]). These bits are used to select the position of
the jitter attenuator.
JAPS1 JAPS0 FUNCTION
0 0 Jitter attenuator is in the receive path.
0 1 Jitter attenuator is in the transmit path.
1 0 Jitter attenuator is not used.
1 1 Jitter attenuator is not used.
Bit 1: T1J1E1 Selection (T1J1E1S). This bit configures the LIU for E1 or T1/J1 operation.
0 = E1
1 = T1 or J1
Bit 0: LOS Criteria Selection (LCS). This bit is used for LIU LOS selection criteria.
E1 Mode:
0 = G.775
1 = ETS 300 233
T1/J1 Mode:
0 = T1.231
1 = T1.231