Datasheet

DS26521 Single T1/E1/J1 Transceiver
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Register Name:
TCBR1, TCBR2, TCBR3, TCBR4
Register Description:
Transmit Channel Blocking Registers 1 to 4
Register Address:
1C4h, 1C5h, 1C6h, 1C7h
Bit #
(MSB) (LSB)
Name CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
TCBR1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
TCBR2
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
TCBR3
CH32 CH31 CH30 CH29 CH28 CH27 CH26
CH25
(F-bit)
TCBR4*
(E1 Mode
Only)
Default 0 0 0 0 0 0 0 0
Bits 7 to 0: Transmit Channel Blocking Channels 1 to 32 Control Bits (CH[1:32]).
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
*Note that TCBR4 has two functions:
When 2.048MHz backplane mode is selected, this register allows the user to enable the channel blocking
signal for any of the 32 possible backplane channels.
When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not the
TCHBLK signal will pulse high during the F-bit time:
TCBR4.0 = 0: Do not pulse TCHBLK during the F-bit.
TCBR4.0 = 1: Pulse TCHBLK during the F-bit.
In this mode, TCBR4.1 to TCBR4.7 should be set to 0.